參數(shù)資料
型號(hào): MC56F8347MPY60
廠商: MOTOROLA INC
元件分類: 數(shù)字信號(hào)處理
英文描述: 16-BIT, 120 MHz, OTHER DSP, PQFP160
封裝: LQFP-160
文件頁數(shù): 72/160頁
文件大小: 2217K
代理商: MC56F8347MPY60
56F8347 Signal Pins
568347 Technical Data
19
Preliminary
D7
(GPIOF0)
28
Input/
Output
Input/
Output
Tri-stated
Data Bus — D7 - D15 specify part of the data for external
program or data memory accesses.
Depending upon the state of the DRV bit in the EMI bus
control register (BCR), D7 - D15 are tri-stated when the
external bus is inactive.
Port F GPIO — These nine GPIO pins can be individually
programmed as input or output pins.
At reset, these pins default to data bus functionality.
To deactivate the internal pull-up resistor, clear the
appropriate GPIO bit in the GPIOF_PUR register.
Example: GPIOF0, clear bit 0 in the GPIOF_PUR register.
D8
(GPIOF1)
29
D9
(GPIOF2)
30
D10
(GPIOF3)
32
D11
(GPIOF4)
149
D12
(GPIOF5)
150
D13
(GPIOF6)
151
D14
(GPIOF7)
152
D15
(GPIOF8)
153
RD
52
Output
Tri-stated
Read Enable — RD is asserted during external memory
read cycles. When RD is asserted low, pins D0 - D15
become inputs and an external device is enabled onto the
data bus. When RD is deasserted high, the external data is
latched inside the device. When RD is asserted, it qualifies
the A0 - A16, PS, and DS pins. RD can be connected
directly to the OE pin of a static RAM or ROM.
Depending upon the state of the DRV bit in the EMI bus
control register (BCR), A0 - A23 and EMI control signals
are tri-stated when the external bus is inactive.
To deactivate the internal pull-up resistor, set the CTRL bit
in the SIM_PUDR register.
Table 2-2 56F8347 Signal and Package Information for the 160-Pin LQFP
Signal Name
Pin No.
Type
State
During
Reset
Signal Description
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