參數(shù)資料
型號: MC56F8322MFAE
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數(shù)字信號處理
英文描述: 0-BIT, 120 MHz, OTHER DSP, PQFP48
封裝: ROHS COMPLIANT, LQFP-48
文件頁數(shù): 89/136頁
文件大小: 719K
代理商: MC56F8322MFAE
56F8322 Techncial Data, Rev. 16
56
Freescale Semiconductor
Preliminary
5.4 Block Diagram
Figure 5-1 Interrupt Controller Block Diagram
5.5 Operating Modes
The ITCN module design contains two major modes of operation:
Functional Mode
The ITCN is in this mode by default.
Wait and Stop Modes
During Wait and Stop modes, the system clocks and the 56800E core are turned off. The ITCN will signal
a pending IRQ to the System Integration Module (SIM) to restart the clocks and service the IRQ. An IRQ
can only wake up the core if the IRQ is enabled prior to entering the Wait or Stop mode. Also, the IRQA
signal automatically becomes low-level sensitive in these modes, even if the control register bits are set to
make them falling-edge sensitive. This is because there is no clock available to detect the falling edge.
A peripheral which requires a clock to generate interrupts will not be able to generate interrupts during Stop
mode. The FlexCAN module can wake the device from Stop mode, and a reset will do just that, or IRQA
and IRQB can wake it up.
Priority
Level
2 -> 4
Decode
INT1
Priority
Level
2 -> 4
Decode
INT82
Level 0
82 -> 7
Priority
Encoder
any0
Level 3
82 -> 7
Priority
Encoder
any3
INT
VAB
IPIC
CONTROL
7
PIC_EN
IACK
SR[9:8]
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