參數(shù)資料
型號: MC56F8322MFAE
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數(shù)字信號處理
英文描述: 0-BIT, 120 MHz, OTHER DSP, PQFP48
封裝: ROHS COMPLIANT, LQFP-48
文件頁數(shù): 50/136頁
文件大?。?/td> 719K
代理商: MC56F8322MFAE
56F8322 Techncial Data, Rev. 16
20
Freescale Semiconductor
Preliminary
EXTAL
(GPIOC0)
32
Input/
Schmitt
Input/
Output
Input
External Crystal Oscillator Input — This input can be connected to
an 8MHz external crystal. If an external clock is used, XTAL must be
used as the input and EXTAL connected to VSS.
The input clock can be selected to provide the clock directly to the
core. This input clock can also be selected as the input clock for the
on-chip PLL.
Port C GPIO — This GPIO pin can be individually programmed as an
input or output pin.
After reset, the default state is an EXTAL input with pull-ups disabled.
XTAL
(GPIOC1)
33
Output
Schmitt
Input/
Output
Crystal Oscillator Output — This output connects the internal crystal
oscillator output to an external crystal.
If an external clock is used, XTAL must be used as the input and
EXTAL connected to VSS.
The input clock can be selected to provide the clock directly to the
core. This input clock can also be selected as the input clock for the
on-chip PLL.
Port C GPIO — This GPIO pin can be individually programmed as an
input or output pin.
After reset, the default state is an XTAL input with pull-ups disabled.
TCK
39
Schmitt
Input
Input, pulled
low internally
Test Clock Input — This input pin provides a gated clock to
synchronize the test logic and shift serial data to the JTAG/EOnCE
port. The pin is connected internally to a pull-down resistor. A Schmitt
trigger input is used for noise immunity.
TMS
40
Schmitt
Input
Input, pulled
high
internally
Test Mode Select Input — This input pin is used to sequence the
JTAG TAP controller’s state machine. It is sampled on the rising edge
of TCK and has an on-chip pull-up resistor.
Note:
Always tie the TMS pin to VDD through a 2.2K resistor.
TDI
41
Schmitt
Input
Input, pulled
high
internally
Test Data Input — This input pin provides a serial input data stream
to the JTAG/EOnCE port. It is sampled on the rising edge of TCK and
has an on-chip pull-up resistor.
TDO
42
Output
In reset,
output is
disabled,
pull-up is
enabled
Test Data Output — This tri-stateable output pin provides a serial
output data stream from the JTAG/EOnCE port. It is driven in the
shift-IR and shift-DR controller states, and changes on the falling edge
of TCK.
Table 2-2 Signal and Package Information for the 48-Pin LQFP (Continued)
Signal Name
Pin No.
Type
State During
Reset
Signal Description
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