參數(shù)資料
型號: MC56F8322MFAE
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數(shù)字信號處理
英文描述: 0-BIT, 120 MHz, OTHER DSP, PQFP48
封裝: ROHS COMPLIANT, LQFP-48
文件頁數(shù): 103/136頁
文件大?。?/td> 719K
代理商: MC56F8322MFAE
Register Descriptions
56F8322 Technical Data, Rev. 16
Freescale Semiconductor
69
Preliminary
5.6.8.5
Timer C, Channel 1 Interrupt Priority Level (TMRC1 IPL)—Bits 1–0
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.9
Interrupt Priority Register 8 (IPR8)
Figure 5-11 Interrupt Priority Register 8 (IPR8)
5.6.9.1
SCI0 Receiver Full Interrupt Priority Level (SCI0_RCV IPL)—
Bits 15–14
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.9.2
SCI0 Receiver Error Interrupt Priority Level (SCI0_RERR IPL)—
Bits 13–12
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.9.3
Reserved—Bits 11–10
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
Base + $8
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
SCI0_RCV
IPL
SCI0_RERR
IPL
0
SCI0_TIDL
IPL
SCI0_XMIT
IPL
TMRA3 IPL
TMRA2 IPL
TMRA1 IPL
Write
RESET
00000
0000000
0000
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