參數(shù)資料
型號: MC56F8146VFVE
廠商: Freescale Semiconductor
文件頁數(shù): 58/178頁
文件大?。?/td> 0K
描述: IC DSP 16BIT 40MHZ 144-LQFP
標準包裝: 60
系列: 56F8xxx
核心處理器: 56800E
芯體尺寸: 16-位
速度: 40MHz
連通性: EBI/EMI,SCI,SPI
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 62
程序存儲器容量: 128KB(64K x 16)
程序存儲器類型: 閃存
RAM 容量: 4K x 16
電壓 - 電源 (Vcc/Vdd): 2.25 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x12b
振蕩器型: 外部
工作溫度: -40°C ~ 105°C
封裝/外殼: 144-LQFP
包裝: 托盤
56F8346 Technical Data, Rev. 15
150
Freescale Semiconductor
Preliminary
10.9 Reset, Stop, Wait, Mode Select, and Interrupt Timing
3. Substitute BMDAR for MDAR if there is no chip select
4. MDAR is active in this calculation only when the chip select changes.
Table 10-17 Reset, Stop, Wait, Mode Select, and Interrupt Timing1,2
1. In the formulas, T = clock cycle. For an operating frequency of 60MHz, T = 16.67ns. At 8MHz (used during Reset and Stop
modes), T = 125ns.
2. Parameters listed are guaranteed by design.
Characteristic
Symbol
Typical
Min
Typical
Max
Unit
See Figure
RESET Assertion to Address, Data and Control Signals
High Impedance
tRAZ
—21
ns
Minimum RESET Assertion Duration
tRA
16T
ns
RESET Deassertion to First External Address Output3
3. During Power-On Reset, it is possible to use the device’s internal reset stretching circuitry to extend this period to 221T.
tRDA
63T
64T
ns
Edge-sensitive Interrupt Request Width
tIRW
1.5T
ns
IRQA, IRQB Assertion to External Data Memory Access
Out Valid, caused by first instruction execution in the
interrupt service routine
tIDM
18T
ns
tIDM - FAST
14T
IRQA, IRQB Assertion to General Purpose Output Valid,
caused by first instruction execution in the interrupt
service routine
tIG
18T
ns
tIG - FAST
14T
Delay from IRQA Assertion (exiting Wait) to External Data
Memory access4
4. The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This is
not the minimum required so that the IRQA interrupt is accepted.
tIRI
22T
ns
tIRI - FAST
18T
Delay from IRQA Assertion to External Data Memory
Access (exiting Stop)
tIF
22T
ns
tIF - FAST
18T
IRQA Width Assertion to Recover from Stop State5
5. The interrupt instruction fetch is visible on the pins only in Mode 3.
tIW
1.5T
ns
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