參數資料
型號: MC56F8146VFVE
廠商: Freescale Semiconductor
文件頁數: 114/178頁
文件大?。?/td> 0K
描述: IC DSP 16BIT 40MHZ 144-LQFP
標準包裝: 60
系列: 56F8xxx
核心處理器: 56800E
芯體尺寸: 16-位
速度: 40MHz
連通性: EBI/EMI,SCI,SPI
外圍設備: POR,PWM,WDT
輸入/輸出數: 62
程序存儲器容量: 128KB(64K x 16)
程序存儲器類型: 閃存
RAM 容量: 4K x 16
電壓 - 電源 (Vcc/Vdd): 2.25 V ~ 3.6 V
數據轉換器: A/D 16x12b
振蕩器型: 外部
工作溫度: -40°C ~ 105°C
封裝/外殼: 144-LQFP
包裝: 托盤
56F8346 Technical Data, Rev. 15
40
Freescale Semiconductor
Preliminary
Part 3 On-Chip Clock Synthesis (OCCS)
3.1 Introduction
Refer to the OCCS chapter of the 56F8300 Peripheral User Manual for a full description of the OCCS.
The material contained here identifies the specific features of the OCCS design. Figure 3-1 shows the
specific OCCS block diagram to reference in the OCCS chapter in the 56F8300 Peripheral User Manual.
Figure 3-1 OCCS Block Diagram
3.2 External Clock Operation
The system clock can be derived from an external crystal, ceramic resonator, or an external system clock
signal. To generate a reference frequency using the internal oscillator, a reference crystal or ceramic
resonator, must be connected between the EXTAL and XTAL pins.
3.2.1
Crystal Oscillator
The internal oscillator is designed to interface with a parallel-resonant crystal resonator in the frequency
range specified for the external crystal in Table 10-15. A recommended crystal oscillator circuit is shown
in Figure 3-2. Follow the crystal supplier’s recommendations when selecting a crystal, since crystal
parameters determine the component values required to provide maximum stability and reliable start-up.
MUX
EXTAL
XTAL
FE
ED
BA
CK
LCK
Prescaler CLK
Postscaler CLK
FOUT/2
Crystal
OSC
Loss of
Reference
Clock
Detector
Lock
Detector
ZSRC
Bus Interface & Control
FOUT
F
REF
PLLDB
PLLCOD
PLLCID
Bus
Interface
Loss of Reference
Clock Interrupt
SYS_CLK2
Source to SIM
MUX
CLKMODE
÷2
Prescaler
÷ (1,2,4,8)
Postscaler
÷ (1,2,4,8)
MS
TR
_O
SC
PLL
x (1 to 128)
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