
56F8346 Technical Data, Rev. 15
136
Freescale Semiconductor
Preliminary
Part 9 Joint Test Action Group (JTAG)
9.1 JTAG Information
Please
contact
your
Freescale
marketing
representative
or
authorized
distributor
for
device/package-specific BSDL information.
Part 10 Specifications
10.1 General Characteristics
The 56F8346/56F8146 are fabricated in high-density CMOS with 5V-tolerant TTL-compatible digital
inputs. The term “5V-tolerant” refers to the capability of an I/O pin, built on a 3.3V-compatible process
technology, to withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture
of devices designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V- and
GPIOF
0
Peripheral
D7
28
1
Peripheral
D8
29
2
Peripheral
D9
30
3
Peripheral
D10
32
4
Peripheral
D11
133
5
Peripheral
D12
134
6
Peripheral
D13
135
7
Peripheral
D14
136
8
Peripheral
D15
137
9
Peripheral
D0
59
10
Peripheral
D1
60
11
Peripheral
D2
72
12
Peripheral
D3
75
13
Peripheral
D4
76
14
Peripheral
D5
77
15
Peripheral
D6
78
1. See Part 6.5.8 to determine how to select peripherals from this set; DEC1 is the selected peripheral at reset .
Table 8-3 GPIO External Signals Map (Continued)
Pins in shaded rows are not available in 56F8346/56F8146
Pins in italics are NOT available in the 56F8146 device
GPIO Port
GPIO Bit
Reset
Function
Functional Signal
Package Pin