參數(shù)資料
型號： MC56F8023VLC
廠商： Freescale Semiconductor
文件頁數(shù)： 27/157頁
文件大?。?/td> 0K
描述： IC DSP 16BIT DUAL HARV 32-LQFP
標(biāo)準(zhǔn)包裝： 1,250
系列： 56F8xxx
核心處理器： 56800E
芯體尺寸： 16-位
速度： 32MHz
連通性： I²C，LIN，SCI，SPI
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 26
程序存儲器容量： 32KB（16K x 16）
程序存儲器類型： 閃存
RAM 容量： 2K x 16
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 6x12b; D/A 2x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 105°C
封裝/外殼： 32-LQFP
包裝： 托盤
56F8033/56F8023 Data Sheet, Rev. 6
122
Freescale Semiconductor
10.2.1
Voltage Regulator Specifications
The 56F8033/56F8023 has two on-chip regulators. One supplies the PLL and relaxation oscillator. It has
no external pins and therefore has no external characteristics which must be guaranteed (other than proper
operation of the device). The second regulator supplies approximately 2.5V to the 56F8033/56F8023’s
core logic. This regulator requires an external 4.4F, or greater, capacitor for proper operation. Ceramic
and tantalum capacitors tend to provide better performance tolerances. The output voltage can be
STANDBY > STOP
100kHz Device Clock
Relaxation Oscillator in Standby mode
PLL powered off
Processor Core in STOP state
All peripheral module and core clocks are off
ADC/DAC/Comparator powered off
Voltage regulator in Standby mode
540
μA0μA
650
μA1μA
POWERDOWN
Device Clock is off
Relaxation Oscillator powered off
PLL powered off
Processor Core in STOP state
All peripheral module and core clocks are off
ADC /DAC/Comparator powered off
Voltage Regulator in Standby mode
440
μA0μA
550
μA1μA
1. No Output Switching
All ports configured as inputs
All inputs Low
No DC Loads
Table 10-7 Power-On Reset Low-Voltage Parameters
Characteristic
Symbol
Min
Typ
Max
Unit
Low-Voltage Interrupt for 3.3V supply1
1. When VDD drops below VEI3.3, an interrupt is generated.
VEI3.3
2.58
2.7
—
V
Low-Voltage Interrupt for 2.5V supply2
2. When VDD drops below VEI32.5, an interrupt is generated.
VE12.5
—2.15—
V
Low-Voltage Interrupt Recovery Hysteresis
VEIH
—50
—
mV
Power-On Reset3
3. Power-On Reset occurs whenever the internally regulated 2.5V digital supply drops below 1.8V. While
power is ramping up, this signal remains active for as long as the internal 2.5V is below 2.15V or the 3.3V
1/O voltage is below 2.7V, no matter how long the ramp-up rate is. The internally regulated voltage is
typically 100mV less than VDD during ramp-up until 2.5V is reached, at which time it self-regulates.
POR
—
1.8
1.9
V
Table 10-6 Current Consumption per Power Supply Pin (Continued)
Mode
Conditions
Typical @ 3.3V, 25°C
Maximum@ 3.6V, 25°C
IDD
1
IDDA
IDD
1
IDDA
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