參數(shù)資料
型號： MC56F8023VLC
廠商： Freescale Semiconductor
文件頁數(shù)： 142/157頁
文件大小： 0K
描述： IC DSP 16BIT DUAL HARV 32-LQFP
標準包裝： 1,250
系列： 56F8xxx
核心處理器： 56800E
芯體尺寸： 16-位
速度： 32MHz
連通性： I²C，LIN，SCI，SPI
外圍設備： POR，PWM，WDT
輸入/輸出數(shù)： 26
程序存儲器容量： 32KB（16K x 16）
程序存儲器類型： 閃存
RAM 容量： 2K x 16
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 6x12b; D/A 2x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 105°C
封裝/外殼： 32-LQFP
包裝： 托盤
Register Descriptions
56F8033/56F8023 Data Sheet, Rev. 6
Freescale Semiconductor
85
peripherals clocks have the option to be clocked at 3X system clock rate, which has a maximum of 96MHz,
if the PLL output clock is selected as the system clock. If PLL is disabled, the 3X system clock will not be
available. This register is used to enable high-speed clocking for those peripherals that support it.
Note:
Operation is unpredictable if peripheral clocks are reconfigured at runtime, so peripherals should be
disabled before a peripheral clock is reconfigured.
Figure 6-9 Peripheral Clock Rate Register (SIM_PCR)
6.3.8.1
Reserved—Bit 15
This bit field is reserved. It must be set to 0.
6.3.8.2
Quad Timer A Clock Rate (TMRA_CR)—Bit 14
This bit selects the clock speed for the Quad Timer A module.
0 = Quad Timer A clock rate equals the system clock rate, to a maximum 32MHz (default)
1 = Quad Timer A clock rate equals 3X system clock rate, to a maximum 96MHz
6.3.8.3
Pulse Width Modulator Clock Rate (PWM_CR)—Bit 13
This bit selects the clock speed for the PWM module.
0 = PWM module clock rate equals the system clock rate, to a maximum 32MHz (default)
1 = PWM module clock rate equals 3X system clock rate, to a maximum 96MHz
6.3.8.4
Inter-Integrated Circuit Run Clock Rate (I2C_CR)—Bit 12
This bit selects the clock speed for the I2C run clock.
0 = I2C module run clock rate equals the system clock rate, to a maximum 32MHz (default)
1 = I2C module run clock rate equals 3X system clock rate, to a maximum 96MHz
6.3.8.5
Reserved—Bits 11–0
This bit field is reserved. Each bit must be set to 0.
6.3.9
Peripheral Clock Enable Register 0 (SIM_PCE0)
The Peripheral Clock Enable register enables or disables clocks to the peripherals as a power savings
feature. Significant power savings are achieved by enabling only the peripheral clocks that are in use.
When a peripheral’s clock is disabled, that peripheral is in Stop mode. Accesses made to a module that has
its clock disabled will have no effect. The corresponding peripheral should itself be disabled while its clock
is shut off. IPBus writes are not possible.
Base + $B
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
TMRA_
CR
PWM_
CR
I2C_
CR
0
Write
RESET
0
000
0
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