參數(shù)資料
型號： MC56F8023VLC
廠商： Freescale Semiconductor
文件頁數(shù)： 146/157頁
文件大?。?/td> 0K
描述： IC DSP 16BIT DUAL HARV 32-LQFP
標(biāo)準(zhǔn)包裝： 1,250
系列： 56F8xxx
核心處理器： 56800E
芯體尺寸： 16-位
速度： 32MHz
連通性： I²C，LIN，SCI，SPI
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 26
程序存儲器容量： 32KB（16K x 16）
程序存儲器類型： 閃存
RAM 容量： 2K x 16
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 6x12b; D/A 2x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 105°C
封裝/外殼： 32-LQFP
包裝： 托盤
Register Descriptions
56F8033/56F8023 Data Sheet, Rev. 6
Freescale Semiconductor
89
6.3.11.2
Comparator A Clock Stop Disable (CMPA_SD)—Bit 14
0 = The clock is disabled during Stop mode
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0
register
6.3.11.3
Digital-to-Analog Converter 0 Clock Stop Disable (DAC1_SD)—Bit 13
0 = The clock is disabled during Stop mode
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0
register
6.3.11.4
Digital-to-Analog Converter 0 Clock Stop Disable (DAC0_SD)—Bit 12
0 = The clock is disabled during Stop mode
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0
register
6.3.11.5
Reserved—Bit 11
This bit field is reserved. It must be set to 0.
6.3.11.6
Analog-to-Digital Converter Clock Stop Disable (ADC_SD)—Bit 10
0 = The clock is disabled during Stop mode
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0
register
6.3.11.7
Reserved—Bits 9–7
This bit field is reserved. Each bit must be set to 0.
6.3.11.8
Inter-Integrated Circuit Clock Stop Disable (I2C_SD)—Bit 6
0 = The clock is disabled during Stop mode
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0
register
6.3.11.9
Reserved—Bit 5
This bit field is reserved. It must be set to 0.
6.3.11.10 QSCI0 Clock Stop Disable (QSCI0_SD)—Bit 4
0 = The clock is disabled during Stop mode
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0
register
6.3.11.11 Reserved—Bit 3
This bit field is reserved. It must be set to 0.
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