MultiMediaCard
TM
98
Sep.22.2005
Revision 0.3
7.22 Card Registers
In SPI mode, only the OCR, CSD and CID registers are accessible. Their format is identical to the format in the MultiMedi-
aCard mode. However, a few fields are irrelevant in SPI mode.
7.23 SPI Bus Timing Diagrams
All timing diagrams use the following schematics and abbreviations:
All timing values are defined in Table7-9. The host must keep the clock running for at least N
CR
clock cycles after receiving
the card response. This restriction applies to both command and data response tokens.
7.23.1 Command / Response
Host Command to Card Response - Card is ready
The following timing diagram describes the basic command response (no data) SPI transaction.
Figure
7-15
: SPI Command/Response Transaction, Card Is Ready
Host Command to Card Response - card is busy
The following timing diagram describes the command response transaction for commands when the card response is of
type R1b (e.g. SET_WRITE_PROT and ERASE). When the card is signaling busy, the host may deselect it (by raising the
CS) at any time. The card will release the DataOut line one clock after the CS going high. To check if the card is still busy,
it needs to be reselected by asserting (set to low) the CS signal. The card will resume busy signal (pulling DataOut low)
one clock after the falling edge of CS.
Symbol
Definition
H
Signal is high (logical ‘1’
L
Signal is low (logical ‘0’)
X
Don’t care (Undefined Value)
Z
High impedance state (-> = 1)
*
Repeater
Busy
Busy Token
Command
Command token
Response
Response token
Data block
Data token
CS
H H L L L
←
N
CS
→
X X
H * * H
* * * * * * * * * * * * * * * * * * * *
L L L L H H H
←
N
EC
→
H * * H
DataIN
6 Bytes Command
H H H H H
←
N
CR
→
H H * * * H
* * * * * * * * *
X X X
DataOut
Z Z Z H H H H
* * * * * * * * *
1 or 2 Bytes Response
H H H H H Z Z