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參數(shù)資料
| 型號： | MC4GH01GNMCA-2SA00 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | SAMSUNG MultiMediaCard |
| 中文描述： | 三星多媒體 |
| 文件頁數(shù)： | 49/102頁 |
| 文件大小： | 1384K |
| 代理商： | MC4GH01GNMCA-2SA00 |
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MultiMediaCard
TM
49
Sep.22.2005
Revision 0.3
Programming of the CID and CSD registers does not require a previous block length setting. The transferred data is also
CRC protected. If a part of the CSD or CID register is stored in ROM, then this unchangeable part must match the corre-
sponding part of the receive buffer. If this match fails, then the card will report an error and not change any register con-
tents.
Some cards may require long and unpredictable times to write a block of data. After receiving a block of data and complet-
ing the CRC check, the card will begin writing and hold the DAT0 line low if its write buffer is full and unable to accept new
data from a new WRITE_BLOCK command. The host may poll the status of the card with a SEND_STATUS command
(CMD13) at any time, and the card will respond with its status. The status bit READY_FOR_DATA indicates whether the
card can accept new data or whether the write process is still in progress). The host may deselect the card by issuing
CMD7 which will displace the card into the
Disconnect State
and release the DAT0 line without interrupting the write oper-
ation. When reselecting the card, it will reactivate busy indication by pulling DAT0 to low if programming is still in progress
and the write buffer is unavailable.
6.2.8 CSD Programming
Programming of the CSD register does not require a previous block length setting. After sending CMD27 and receiving an
R1 response, the start bit (=0)is sent, the modified CSD register (=16 bytes), CRC16 (=2bytes), and end bit (=1). The host
can change only the least significant 16bits [15:0] of the CSD. The rest of the CSD register content must match the Multi-
MediaCard CSD Register. If the card detects a content inconsistency between the old and new CSD register, it will not
reprogram the CSD in order to ensure validity of the CRC field in the CSD register.
Bits [7:1] are the CRC7 of bits [127:8] of the CSD register, which should be recalculated once the register changes. After
calculating CRC7, the CRC16 should also be calculated for all of the CSD register [127:0].
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