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Chapter 16 S12X Debug (S12XDBGV3) Module
MC9S12XF - Family Reference Manual, Rev.1.19
Freescale Semiconductor
785
and generating a breakpoint, if breakpoints are enabled. External tagging is only possible in device
emulation modes.
16.4.3.4
Trigger On XGATE S/W Breakpoint Request
The XGATE S/W breakpoint request issues a forced breakpoint request to the CPU12X immediately
independent of S12XDBG settings and triggers the state sequencer into the disarmed state. Active tracing
sessions are terminated immediately, thus if tracing has not yet begun, no trace information is stored.
XGATE generated breakpoints are independent of the DBGBRK bits. The XGSBPE bit in DBGC1
determines if the XGATE S/W breakpoint function is enabled. The BDM bit in DBGC1 determines if the
XGATE requested breakpoint causes the system to enter BDM Mode or initiate a software interrupt (SWI).
16.4.3.5
TRIG Immediate Trigger
Independent of comparator matches or external tag signals it is possible to initiate a tracing session and/or
breakpoint by writing the TRIG bit in DBGC1 to a logic “1”. If congured for begin or mid aligned tracing,
this triggers the state sequencer into the Final State, if congured for end alignment, setting the TRIG bit
disarms the module, ending the session. If breakpoints are enabled, a forced breakpoint request is issued
immediately (end alignment) or when tracing has completed (begin or mid alignment).
16.4.3.6
Trigger Priorities
In case of simultaneous triggers, the priority is resolved according to
Table 16-41. The lower priority
trigger is suppressed. It is thus possible to miss a lower priority trigger if it occurs simultaneously with a
trigger of a higher priority. The trigger priorities described in
Table 16-41 dictate that in the case of
simultaneous matches, the match on the lower channel number (0,1,2,3) has priority. The SC[3:0]
encoding ensures that a match leading to nal state has priority over all other matches independent of
current state sequencer state. When congured for range modes a simultaneous match of comparators A
and C generates an active match0 whilst match2 is suppressed.
If a write access to DBGC1 with the ARM bit position set occurs simultaneously to a hardware disarm
from an internal trigger event, then the ARM bit is cleared due to the hardware disarm.
Table 16-41. Trigger Priorities
Priority
Source
Action
Highest
XGATE
Immediate forced breakpoint......(Tracing terminated immediately).
TRIG
Trigger immediately to nal state (begin or mid aligned tracing enabled)
Trigger immediately to state 0 (end aligned or no tracing enabled)
External TAGHI/TAGLO
Enter State0
Match0 (force or tag hit)
Trigger to next state as dened by state control registers
Match1 (force or tag hit)
Trigger to next state as dened by state control registers
Match2 (force or tag hit)
Trigger to next state as dened by state control registers
Lowest
Match3 (force or tag hit)
Trigger to next state as dened by state control registers