LOGIC COMMANDS AND REGISTERS LPC REGISTER D" />
參數(shù)資料
型號: MC33889BDW
廠商: Freescale Semiconductor
文件頁數(shù): 44/59頁
文件大小: 0K
描述: IC SYSTEM BASE W/CAN 28-SOIC
標準包裝: 1
控制器類型: 系統(tǒng)基礎芯片
接口: CAN
電源電壓: 5.5 V ~ 18 V
電流 - 電源: 45mA
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
供應商設備封裝: 28-SOIC W
包裝: 管件
Analog Integrated Circuit Device Data
Freescale Semiconductor
49
33889
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
LPC REGISTER
Description: This register controls:
The state of HS1 in Stop and Sleep mode (HS1 permanently off or HS1 cyclic)
Enable or disable the forced wake-up function (SBC automatic wake-up after time spend in Sleep or Stop mode, time
defined by the TIM2 register)
Enable or disable the sense of the wake-up inputs (LX) at sampling point of the cyclic sense period (LX2HS1 bit).
Table 27. LPC Register
LPC
D3
D2
D1
D0
$110b
W
LX2HS1
FWU
IDDS
HS1AUTO
R
Reset
0
Reset condition
POR, NR2R, N2R, STB2R,
STO2R
POR, NR2R, N2R, STB2R,
STO2R
POR, NR2R, N2R, STB2R,
STO2R
POR, NR2R, N2R, STB2R,
STO2R
LX2HS1
HS1AUTO
Wake-up Inputs Supplied by HS1
Autotiming HS1
X
0
off
X
1
On, HS1 cyclic, period defined in TIM2 register
0
X
no
1
X
Yes, LX inputs sensed at sampling point
Bit
Description
FWU
If this bit is set, and the SBC is turned into sleep or stop mode, the SBC wakes up after the time selected in the TIM2 register
IDDS
Bit = 0: IDDS-WU1 selected (lowest value, typ 3.5 mA)
Bit = 1: IDDS-WU2 selected (highest value, typ 14 mA)
Table 28. INTR register
INTR
D3
D2
D1
D0
$111b
W
VSUPLOW
HS1OT-V2LOW
VDDTEMP
CANF
R
VSUPLOW
HS1OT
VDDTEMP
CANF
Reset
0
Reset condition
POR, RESET
Cyclic sense timing
Cyclic sense on time
t
HS1
Sample
10
s to 20 s
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