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參數(shù)資料
| 型號(hào)： | MC10E197 |
| 廠商： | ON SEMICONDUCTOR |
| 英文描述： | DATA SEPARATOR |
| 中文描述： | 數(shù)據(jù)分離器 |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 217K |
| 代理商： | MC10E197 |
MC10E197
MOTOROLA
ECLinPS and ECLinPS Lite
DL140 — Rev 4
2–4
RDATA
RDATA
RDCLK
RDCLK
tS
tH
SETUP AND HOLD TIMING DIAGRAMS
APPLICATIONS INFORMATION
General Operation
Operation
The E197 is a phase-locked loop circuit consisting of an
internal VCO, a Data Phase detector with associated
acquisition circuitry, and a Phase/Frequency detector (Figure
1). In addition, an enable pin(ENVCO) is provided to disable
the internal VCO and enable the external VCO input. Hence,
the user has the option of supplying the VCO signal.
The E197 contains two phase detectors: a data phase
detector for synchronizing to the non-periodic pulses in the
read data stream during the data read mode of operation, and
a phase/ frequency detector for frequency (and phase) locking
to an external reference clock during the “idle” mode of
operation. The read enable (RDEN) pin muxes between these
two detectors.
Data Read Mode
The data pins (RAWD) are enabled when the RDEN pin is
placed at a logic high level, thus enabling the Data Phase
detector (Figure1) and initiating the data read mode. In this
mode, the loop is servoed by the timing information taken from
the positive edges of the input data pulses. This phase
detector samples positive edges from the RAWD signal and
generates both a pump up and pump down pulse from any
edge of the input data pulse. The leading edge of the pump up
pulse is time modulated by the leading edge of the data signal,
whereas the rising edge of the pump up pulse is generated
synchronous to the VCO clock. The falling edge of the pump
down pulse is synchronous to the falling edge of the VCO
clock and the rising edge of the pump down signal is
synchronous to the rising edge of the VCO clock. Since both
edges of the VCO are used the internal clock a duty cycle of
50%. This pulse width modulation technique is used to
generate the servoing signal which drives the VCO. The pump
down signal is a reference pulse which is included to provide
an evenly balanced differential system, thereby allowing the
synthesis of a VCO input control signal after appropriate signal
processing by the loop filter.
By using suitable external filter circuitry, a control signal for
input into the VCO can be generated by inverting the pump
down signal, summing the inverted signal with the pump up
signal and averaging the result. The polarity of this control
signal is defined as zero when the data edges lead the clock
by a half clock cycle. If the data edges are advanced with
respect to the zero polarity data/VCO edge relationship, the
control signal is defined to have a negative polarity; whereas
if the VCO is advanced with respect to the zero polarity
data/VCO edge relationship, the control signal is defined to
have a positive polarity. If there is no data edge present at the
RAWD input, the corresponding pump up and pump down
outputs are not generated and the resulting control output is
zero.
Acquisition Circuitry
The acquisition circuitry is provided to assist the data phase
detector in phase locking to the sync field that precedes the
data. For the case in which lock-up is attempted when the data
edges are coincident with the VCO edges, the pump down
signal may enter an indeterminate state for an unacceptably
long period due to the violation of internal set up and hold
times. After an initial pump down pulse, the circuit blocks
successive pump down pulses, and inserts extra pump up
pulses, during portions of the sync field that are known to
contain zeros. Thus, the data phase detector is forced to have
a nonzero output during the lock-up period, and the restoring
force ensures correction of the loop within an acceptable time.
Hence, this circuitry provides a quasi-deterministic pump
down output signal, under the condition of coincident data and
VCO edges, allowing lock-up to occur with excessive delays.
The ACQ line is provided to disable (disable = HIGH) the
acquisition circuit during the data portion of a sector block.
Typically, this circuit is enabled at the beginning of the sync
field by a one-shot timer to ensure a timely lock-up.
The TYPE line allows the choice between two sync field
preamble types; transitions interspersed with two zeros
between transitions. These types of sync fields are used with
the 1:7 and 2:7 coding schemes, respectively.
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| MC10E197FN | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC10E211 C14N WAF | 制造商:ON Semiconductor 功能描述: |
| MC10E211FN | 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 5V ECL 1:6 Diff RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| MC10E211FNG | 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 5V ECL 1:6 Diff Clock Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| MC10E211FNR2 | 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 5V ECL 1:6 Diff RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
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