參數(shù)資料
型號： MC10129L
廠商： MOTOROLA INC
元件分類： 通用總線功能
英文描述： Parallel-Load 8-Bit Shift Registers 16-CDIP -55 to 125
中文描述： LINE RECEIVER, CDIP16
封裝： CERAMIC, DIP-16
文件頁數(shù)： 4/7頁
文件大?。?/td> 110K
代理商： MC10129L
MC10129
MOTOROLA
MECL Data
DL122 — Rev 6
3–4
ELECTRICAL CHARACTERISTICS
TEST VOLTAGE VALUES
(Volts)
IBM INPUT LEVELS
(
6.
)
HYSTERESIS MODE
@ Test Temperature
VIH
3.11
VIL
0.150
VIHA
′
VILA
′
VIHA
′′
2.90
VILA
′′
2.00
VIHA
′′′
2.20
VILA
′′′
1.30
VCC
(
5.
)
+5.0
VEE
–5.2
–30
°
C
+25
°
C
+85
°
C
3.11
0.150
1.700
0.70
2.60
1.70
1.90
1.00
+5.0
–5.2
3.11
0.150
2.30
1.40
1.60
0.70
+5.0
–5.2
Pin
Under
Test
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
Characteristic
Symbol
VIH
VIL
VIHA
′
VILA
′
VIHA
′′
VILA
′′
VIHA
′′′
VILA
′′′
VCC
(
5.
)
VEE
Gnd
Negative Power Supply
Drain Current
IE
8
8
9
9
8
5,8
1,5,16
1,16
Positive Power Supply
Drain Current
ICC
9
4,6,
7,13
9
9
5,8
5,8
1,16
1,16
Input Current
IinH
4
6
7
10
11
12
13
4
6
7
13
9
9
9
9
9
9
9
8
8
8
8
8
8
8
1,16
1,16
1,16
1,16
1,16
1,16
1,16
ICBO
(
1.
)
4
6
7
13
4
6
7
13
9
9
9
9
8
8
8
8
1,16
1,16
1,16
1,16
IinL
10
11
12
9
9
9
8
8
8
1,16
1,16
1,16
Output Voltage
Logic 1
VOH
2
3
2
3
4
6
4
6
9
9
9
9
5,8
5,8
8
8
1,16
1,16
1,5,16
1,5,16
Output Voltage
Logic 0
VOL
2
3
2
3
4
6
4
6
9
9
9
9
5,8
5,8
8
8
1,16
1,16
1,5,16
1,5,16
Threshold Voltage
Logic 1
VOHA
2
(
2.
)
2
2
2
2
(
3.
)
2
(
4.
)
4
4
4
4
4
4
9
9
9
9
9
9
5,8
5,8
5,8
5,8
8
8
1,16
1,16
1,16
1,16
1,5,16
1,5,16
Threshold Voltage
Logic 0
VOLA
2
(
2.
)
2
2
(
2.
)
2
2
(
3.
)
2
(
4.
)
4
4
4
4
4
4
9
9
9
9
9
9
5,8
5,8
5,8
5,8
8
8
1,16
1,16
1,16
1,16
1,5,16
1,5,16
Switching Times
Propagation Delay
+5.0V
+2.40V
Figure
+7.0V
–3.2V
+2.0V
Data Input
t7+14+
t7–14–
t11–14+
t11–14–
t12+14+
t12–14–
t10+14–
t7+14+
t7–14–
tsetup
thold
t+
t–
14
14
14
14
14
14
14
14
14
14
14
14
14
Figure 3
Figure 3
Figure 6
Figure 6
Figure 4
Figure 4
Figure 5
Figure 3
Figure 3
Figure 7
Figure 7
Figure 3
Figure 3
9
9
9
9
9
9
9
9
9
9
9
9
9
5,8
5,8
5,8
5,8
5,8
5,8
5,8
8
8
5,8
5,8
5,8
5,8
1,16
1,16
1,16
1,16
1,16
1,16
1,16
1,5,16
1,5,16
1,16
1,16
1,16
1,16
Clock Input
Strobe Input
7
7
7
Reset Input
Hysteresis Mode
Setup Time
Hold Time
Rise Time
Fall Time
1. Pin 5 to VEE, VIL to Data input one at a time.
2. Output latched to logic high state prior to test. VIHA
′
, VILA
′
are standard logic 1 and logic 0 MTTL threshold voltages. VIHA
′′
, VILA
′′
, VIHA
′′′
and VILA
′′′
are logic 1 and
logic 0 threshold voltages in the hysteresis mode as shown in Figure 1 on page 3–2.
3. Input level on data input taken from +0.4V up to voltage level given.
4. Input level on data input taken from +4.0V down to voltage level given.
5. Operation and limits shown also apply for VCC = +6.0V.
6. When testing, choose either TTL or IBM input levels.
相關(guān)PDF資料
PDF描述
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