參數(shù)資料
型號(hào)： MC10129L
廠商： MOTOROLA INC
元件分類(lèi)： 通用總線功能
英文描述： Parallel-Load 8-Bit Shift Registers 16-CDIP -55 to 125
中文描述： LINE RECEIVER, CDIP16
封裝： CERAMIC, DIP-16
文件頁(yè)數(shù)： 2/7頁(yè)
文件大?。?/td> 110K
代理商： MC10129L
MC10129
MOTOROLA
MECL Data
DL122 — Rev 6
3–2
ELECTRICAL CHARACTERISTICS
Test Limits
Pin
Under
Test
–30
°
C
+25
°
C
+85
°
C
Characteristic
Symbol
Min
Max
Min
Typ
Max
Min
Max
Unit
Negative Power Supply Drain
Current
IE
8
8
167
189
152
172
167
189
mAdc
Positive Power Supply Drain Current
ICC
9
8.0
8.0
8.0
mAdc
Input Current
IinH
4
6
7
10
11
12
13
150
150
150
720
390
390
150
95
95
95
450
245
245
95
95
95
95
450
245
245
95
μ
Adc
ICBO
(
1.
)
4
6
7
13
1.5
1.5
1.5
–1.0
–1.0
–1.0
–1.0
1.0
1.0
1.0
μ
Adc
IinL
10
11
12
0.5
0.5
0.5
0.5
0.5
0.5
0.3
0.3
0.3
μ
Adc
Output Voltage
Logic 1
VOH
2
3
2
3
–1.060
–1.060
–1.060
–1.060
–0.890
–0.890
–0.890
–0.890
–0.960
–0.960
–0.960
–0.960
–0.810
–0.810
–0.810
–0.810
–0.890
–0.890
–0.890
–0.890
–0.700
–0.700
–0.700
–0.700
Vdc
Output Voltage
Logic 0
VOL
2
3
2
3
–1.890
–1.890
–1.890
–1.890
–1.675
–1.675
–1.675
–1.675
–1.850
–1.850
–1.850
–1.850
–1.650
–1.650
–1.650
–1.650
–1.825
–1.825
–1.825
–1.825
–1.615
–1.615
–1.615
–1.615
Vdc
Threshold Voltage
Logic 1
VOHA
2
(
2.
)
2
2
2
2
(
3.
)
2
(
4.
)
–1.080
–1.080
–1.080
–1.080
–1.080
–1.080
–0.980
–0.980
–0.980
–0.980
–0.980
–0.980
–0.910
–0.910
–0.910
–0.910
–0.910
–0.910
Vdc
Threshold Voltage
Logic 0
VOLA
2
(
2.
)
2
2
(
2.
)
2
2
(
3.
)
2
(
4.
)
–1.655
–1.655
–1.655
–1.655
–1.655
–1.655
–1.630
–1.630
–1.630
–1.630
–1.630
–1.630
–1.595
–1.595
–1.595
–1.595
–1.595
–1.595
Vdc
Switching Times
Propagation Delay
Data Input
ns
t7+14+
t7–14–
t11–14+
t11–14–
t12+14+
t12–14–
t10+14–
t7+14+
t7–14–
tsetup
thold
t+
t–
14
14
14
14
14
14
14
14
14
14
14
14
14
3.7
3.7
2.7
2.7
1.6
1.6
2.0
6.6
3.7
30
0
1.5
1.5
15
15
11
11
8.0
8.0
8.0
30
17
3.7
3.7
2.7
2.7
1.6
1.6
2.0
6.7
3.7
2.7
–2.0
1.5
1.5
10
10
5.0
5.0
4.0
4.0
5.0
18
10
15
15
2.0
2.0
15
15
9.0
9.0
7.0
7.0
6.5
25
15
3.7
3.7
2.7
2.7
1.6
1.6
2.0
6.6
3.7
30
–2.0
1.5
1.5
30
40
11
11
8.0
8.0
8.0
30
40
Clock Input
Strobe Input
Reset Input
Hysteresis Mode
Setup Time
Hold Time
Rise Time
Fall Time
5.0
5.0
4.3
4.3
5.0
5.0
1. Pin 5 to VEE, VIL to Data input one at a time.
2. Output latched to logic high state prior to test. VIHA
′
, VILA
′
are standard logic 1 and logic 0 MTTL threshold voltages. VIHA
′′
, VILA
′′
, VIHA
′′′
and VILA
′′′
are logic 1 and
logic 0 threshold voltages in the hysteresis mode as shown in Figure 1 on page 3–2.
3. Input level on data input taken from +0.4V up to voltage level given.
4. Input level on data input taken from +4.0V down to voltage level given.
5. Operation and limits shown also apply for VCC = +6.0V.
VIHA
′′
Vin
Vout
Logic 1
Logic 0
VIHA
′′′
VILA
′′
VILA
′′′
Hysteresis Mode
Threshold Voltage
Figure 1. Hysteresis Mode Threshold Voltage
相關(guān)PDF資料
PDF描述
MC10131FN Parallel-Load 8-Bit Shift Registers 16-CDIP -55 to 125
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