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參數(shù)資料
| 型號： | MC10129L |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | Parallel-Load 8-Bit Shift Registers 16-CDIP -55 to 125 |
| 中文描述： | LINE RECEIVER, CDIP16 |
| 封裝： | CERAMIC, DIP-16 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大?。?/td> | 110K |
| 代理商： | MC10129L |
LOGIC DIAGRAM
VCC = PIN 9
GND = PIN 1 AND 16
VEE = PIN 8
14 Q0
D0
7
D
C
R
15 Q1
D1 13
D
C
R
3
Q2
D2
6
D
C
R
2
Q3
D3
4
D
C
R
HYSTERESIS
CONTROL
CLOCK 11
RESET 10
STROBE 12
5
SEMICONDUCTOR TECHNICAL DATA
3–1
REV 6
Motorola, Inc. 1996
9/96
The MC10129 data inputs are compatible with, and accept TTL logic levels
as well as levels compatible with IBM–type buses. The clock, strobe, and reset
inputs accept MECL 10,000 logic levels.
The data inputs accept the bus levels, and storage elements are provided to
yield temporary latch storage of the information after receiving it from the bus.
The outputs can be strobed to allow accurate synchronization of signals and/or
connection to MECL 10,000 level buses. When the clock is low, and the reset
input is disabled, the outputs will follow the D inputs. The latches will store the
data on the rising edge of the clock. The outputs are enabled when the strobe
input is high. Unused D inputs must be tied to VCC or Gnd. The clock, strobe,
and reset inputs each have 50 k ohm pulldown resistors to VEE. They may be
left floating, if not used.
The MC10129 will operate in either of two modes. The first mode is obtained
by tying the hysteresis control input to VEE. In this mode, the input threshold
points of the D inputs are fixed. The second mode is obtained by tying the
hysteresis control input to ground. In this mode, input hysteresis is achieved as
shown in the test table. This hysteresis is desirable where extra noise margin is
required on the D inputs. The outer input pins are unaffected by the mode of
operation used.
The MC10129 is especially useful in interface applications for central
processors, mini–computers, and peripheral equipment.
PD= 750 mW typ/pkg (No Load)
tpd= 10 ns typ
VCC Max = 7.0 Vdc
TRUTH TABLE
D
X
X
L
X
H
C
X
H
L
H
L
STROBE
L
X
H
H
H
RESET
X
H
X
L
X
Qn + 1
L
L
L
Qn
H
PIN ASSIGNMENT
GND
Q3
Q2
D3
HYSTERESIS
CONTROL
D2
D0
VEE
GND
Q1
Q0
D1
STROBE
CLOCK
RESET
VCC
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
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