參數(shù)資料
型號(hào)： MC10129L
廠商： MOTOROLA INC
元件分類： 通用總線功能
英文描述： Parallel-Load 8-Bit Shift Registers 16-CDIP -55 to 125
中文描述： LINE RECEIVER, CDIP16
封裝： CERAMIC, DIP-16
文件頁數(shù)： 3/7頁
文件大小： 110K
代理商： MC10129L
MC10129
3–3
MOTOROLA
MECL Data
DL122 — Rev 6
ELECTRICAL CHARACTERISTICS
TEST VOLTAGE VALUES
(Volts)
MECL 10,000 INPUT LEVELS
TTL INPUT LEVELS
(
6.
)
@ Test Temperature
VIHmax
–0.890
VILmin
–1.890
VIHAmin
–1.155
VILAmax
–1.500
VIH
3.000
VIL
0.400
VIHA
′
2.000
VILA
′
0.800
–30
°
C
+25
°
C
+85
°
C
–0.810
–1.850
–1.105
–1.475
3.000
0.400
2.000
0.800
–0.700
–1.825
–1.035
–1.440
3.000
0.400
2.000
0.800
Pin
Under
Test
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
Characteristic
Symbol
VIHmax
VILmin
VIHAmin
VILAmax
VIH
VIL
VIHA
′
VILA
′
Gnd
Negative Power Supply
Drain Current
IE
8
8
11
11
12
12
1,5,16
1,16
Positive Power Supply
Drain Current
ICC
9
4,6,7,13
1,16
Input Current
IinH
4
6
7
10
11
12
13
10,11
11
12
4
6
7
13
1,16
1,16
1,16
1,16
1,16
1,16
1,16
ICBO
(
1.
)
4
6
7
13
4
6
7
13
1,16
1,16
1,16
1,16
IinL
10
11
12
10
11
12
1,16
1,16
1,16
Output Voltage
Logic 1
VOH
2
3
2
3
12
12
12
12
10,11
10,11
10,11
10,11
4
6
4
6
1,16
1,16
1,5,16
1,5,16
Output Voltage
Logic 0
VOL
2
3
2
3
12
12
12
12
10,11
10,11
10,11
10,11
4
6
4
6
1,16
1,16
1,5,16
1,5,16
Threshold Voltage
Logic 1
VOHA
2
(
2.
)
2
2
2
2
(
3.
)
2
(
4.
)
11,12
10,12
12
12
12
10,11
10,11
10,11
10,11
12
10
11
4
4
4
4
1,16
1,16
1,16
1,16
1,5,16
1,5,16
Threshold Voltage
Logic 0
VOLA
2
(
2.
)
2
2
(
2.
)
2
2
(
3.
)
2
(
4.
)
11,12
10,12
12
12
12
10,11
10,11
10,11
10,11
10
11
12
4
4
4
4
1,16
1,16
1,16
1,16
1,5,16
1,5,16
Switching Times
Propagation Delay
+1.11V
+0.31V
Pulse In
Pulse
Out
+5.0V
+2.40V
Figure
+2.0V
Data Input
t7+14+
t7–14–
t11–14+
t11–14–
t12+14+
t12–14–
t10+14–
t7+14+
t7–14–
tsetup
thold
t+
t–
14
14
14
14
14
14
14
14
14
14
14
14
14
12
12
12
12
10,11
10,11
10
10
10,11
10,11
7
7
14
14
14
14
14
14
14
14
14
14
14
14
14
Figure 3
Figure 3
Figure 6
Figure 6
Figure 4
Figure 4
Figure 5
Figure 3
Figure 3
Figure 7
Figure 7
Figure 3
Figure 3
1,16
1,16
1,16
1,16
1,16
1,16
1,16
1,5,16
1,5,16
1,16
1,16
1,16
1,16
Clock Input
7,11
7,11
12
12
10,11
7
7
7,11
7,11
7
7
Strobe Input
7
7
7
Reset Input
Hysteresis Mode
12
12
12
12
12
12
12
7
10,11
10,11
10
10
10,11
10,11
Setup Time
Hold Time
Rise Time
Fall Time
1. Pin 5 to VEE, VIL to Data input one at a time.
2. Output latched to logic high state prior to test. VIHA
′
, VILA
′
are standard logic 1 and logic 0 MTTL threshold voltages. VIHA
′′
, VILA
′′
, VIHA
′′′
and VILA
′′′
are logic 1 and
logic 0 threshold voltages in the hysteresis mode as shown in Figure 1 on page 3–2.
3. Input level on data input taken from +0.4V up to voltage level given.
4. Input level on data input taken from +4.0V down to voltage level given.
5. Operation and limits shown also apply for VCC = +6.0V.
6. When testing, choose either TTL or IBM input levels.
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