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參數(shù)資料
| 型號： | MC100EP016A |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 通用總線功能 |
| 英文描述： | 3.3 V ECL 8-Bit Synchronous Binary Up Counter |
| 中文描述： | 3.3伏ECL 8位二進(jìn)制計數(shù)器同步最多 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 98K |
| 代理商： | MC100EP016A |
MC100EP016A
http://onsemi.com
9
Applications Information
(continued)
EP01
Q0 to Q7
P0 to P7
CLK
TC
PE
CE
Figure 6. 32-Bit Cascaded EP016A Programmable Divider
LO
CLK
CLK
CLK
MSB
LSB
EP016
EP01
EP01
Q0 to Q7
Q0 to Q7
Q0 to Q7
P0 to P7
P0 to P7
P0 to P7
EP016
EP016
EP016
CLK
TC
PE
CE
CLK
CLK
TC
PE
CE
CLK
CLK
TC
PE
CE
CLK
Figure 6 shows a typical block diagram of a 32-bit divider
chain. Once again to maximize the frequency of operation
EP01 OR gates were used. For lower frequency applications
a slower OR gate could replace the EP01. Note that for a
16-bit divider the OR function feeding the PE (program
enable) input CANNOT be replaced by a wire OR tie as the
TC output of the least significant EP016A must also feed the
CE input of the most significant EP016A. If the two TC
outputs were OR tied the cascaded count operation would
not operate properly. Because in the cascaded form the PE
feedback is external and requires external gating, the
maximum frequency of operation will be significantly less
than the same operation in a single device.
Maximizing EP016A Count Frequency
The EP016A device produces 9 fast transitioning single
ended outputs, thus V
CC
noise can become significant in
situations where all of the outputs switch simultaneously in
the same direction. This V
CC
noise can negatively impact
the maximum frequency of operation of the device. Since
the device does not need to have the Q outputs terminated to
count properly, it is recommended that if the outputs are not
going to be used in the rest of the system they should be left
unterminated. In addition, if only a subset of the Q outputs
are used in the system only those outputs should be
terminated. Not terminating the unused outputs will not only
cut down the V
CC
noise generated but will also save in total
system power dissipation. Following these guidelines will
allow designers to either be more aggressive in their designs
or provide them with an extra margin to the published data
book specifications.
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PDF描述 |
|---|---|
| MC100EP016AFA | 3.3 V ECL 8-Bit Synchronous Binary Up Counter |
| MC100EP016AFAR2 | 3.3 V ECL 8-Bit Synchronous Binary Up Counter |
| MC100EP40DTG | 3.3V / 5V ECL Differential Phase−Frequency Detector |
| MC100EP40DTR2G | 3.3V / 5V ECL Differential Phase−Frequency Detector |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC100EP016A_06 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:3.3 V ECL 8−Bit Synchronous Binary Up Counter |
| MC100EP016AFA | 功能描述:計數(shù)器移位寄存器 3.3V/5V ECL 8-Bit RoHS:否 制造商:Texas Instruments 計數(shù)器類型: 計數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| MC100EP016AFAG | 功能描述:計數(shù)器移位寄存器 3.3V/5V ECL 8-Bit Up Counter RoHS:否 制造商:Texas Instruments 計數(shù)器類型: 計數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| MC100EP016AFAG | 制造商:ON Semiconductor 功能描述:LOGIC IC |
| MC100EP016AFAR2 | 功能描述:計數(shù)器移位寄存器 3.3V/5V ECL 8-Bit RoHS:否 制造商:Texas Instruments 計數(shù)器類型: 計數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
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