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參數(shù)資料
| 型號(hào)： | MC100EP016AFA |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 通用總線功能 |
| 英文描述： | 3.3 V ECL 8-Bit Synchronous Binary Up Counter |
| 中文描述： | 100E SERIES, SYN POSITIVE EDGE TRIGGERED 8-BIT UP BINARY COUNTER, PQFP32 |
| 封裝： | LQFP-32 |
| 文件頁(yè)數(shù)： | 1/12頁(yè) |
| 文件大?。?/td> | 98K |
| 代理商： | MC100EP016AFA |
Semiconductor Components Industries, LLC, 2004
May 2004 Rev. 4
1
Publication Order Number:
MC100EP016A/D
MC100EP016A
3.3 VECL 8Bit
Synchronous Binary
Up Counter
The MC100EP016A is a highspeed synchronous, presettable,
cascadeable 8bit binary counter. Architecture and operation are the
same as the ECLinPS
family MC100E016 with higher operating
speed.
The counter features internal feedback to TC gated by the TCLD
(Terminal Count Load) pin. When TCLD is LOW (or left open, in
which case it is pulled LOW by the internal pulldowns), the TC
feedback is disabled, and counting proceeds continuously, with TC
going LOW to indicate an allone state. When TCLD is HIGH, the TC
feedback causes the counter to automatically reload upon TC = LOW,
thus functioning as a programmable counter. The Qn outputs do not
need to be terminated for the count function to operate properly. To
minimize noise and power, unused Q outputs should be left
unterminated.
COUT and COUT provide differential outputs from a single,
noncascaded counter or divider application. COUT and COUT
should not be used in cascade configuration. Only TC should be used
for a counter or divider cascade chain output.
A differential clock input has also been added to improve
performance.
The 100 Series contains temperature compensation.
550 ps Typical Propagation Delay
Operation Frequency > 1.3 GHz is 30% Faster than MC100EP016
PECL Mode Operating Range: V
CC
= 3.0 V to 3.6 V
with V
EE
= 0 V
NECL Mode Operating Range: V
CC
= 0 V
with V
EE
= 3.0 V to 3.6 V
Open Input Default State
Safety Clamp on Clock Inputs
Internal TC Feedback (Gated)
Addition of COUT and COUT
8Bit
Differential Clock Input
V
BB
Output
Fully Synchronous Counting and TC Generation
Asynchronous Master Reset
Device
Package
Shipping
ORDERING INFORMATION
LQFP32
FA SUFFIX
CASE 873A
MARKING
DIAGRAM*
MC100
EP016A
AWLYYWW
1
32
A
WL = Wafer Lot
YY
= Year
WW = Work Week
= Assembly Location
*For additional information, see Application Note
AND8002/D
MC100EP016AFA
LQFP32
250 Units/Tray
MC100EP016AFAR2 LQFP32 2000/Tape & Reel
http://onsemi.com
For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
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| MC100EP016AFAR2 | 3.3 V ECL 8-Bit Synchronous Binary Up Counter |
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| MC100EP91DWR2 | 2.5 V/3.3 V Any Level Positive Input to -3.3 V/-5.5 V NECL Output Translator |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC100EP016AFAG | 功能描述:計(jì)數(shù)器移位寄存器 3.3V/5V ECL 8-Bit Up Counter RoHS:否 制造商:Texas Instruments 計(jì)數(shù)器類型: 計(jì)數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時(shí)間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| MC100EP016AFAG | 制造商:ON Semiconductor 功能描述:LOGIC IC |
| MC100EP016AFAR2 | 功能描述:計(jì)數(shù)器移位寄存器 3.3V/5V ECL 8-Bit RoHS:否 制造商:Texas Instruments 計(jì)數(shù)器類型: 計(jì)數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時(shí)間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| MC100EP016AFAR2G | 功能描述:計(jì)數(shù)器 IC 3.3V/5V ECL 8-Bit Up Counter RoHS:否 制造商:NXP Semiconductors 計(jì)數(shù)器類型:Binary Counters 邏輯系列:74LV 位數(shù):10 計(jì)數(shù)法: 計(jì)數(shù)順序: 工作電源電壓:1 V to 5.5 V 工作溫度范圍:- 40 C to + 125 C 封裝 / 箱體:SOT-109 封裝:Reel |
| MC100EP016AMNG | 功能描述:計(jì)數(shù)器移位寄存器 3.3V ECL 8BT COUNTER BBG ECL RoHS:否 制造商:Texas Instruments 計(jì)數(shù)器類型: 計(jì)數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時(shí)間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
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