參數(shù)資料
型號: MC100EP40DTR2G
廠商: ON SEMICONDUCTOR
元件分類: XO, clock
英文描述: 3.3V / 5V ECL Differential Phase−Frequency Detector
中文描述: PHASE DETECTOR, 2000 MHz, PDSO20
封裝: LEAD FREE, TSSOP-20
文件頁數(shù): 1/9頁
文件大小: 140K
代理商: MC100EP40DTR2G
Semiconductor Components Industries, LLC, 2006
November, 2006
Rev. 10
1
Publication Order Number:
MC100EP40/D
MC100EP40
3.3V / 5VECL Differential
PhaseFrequency Detector
Description
The MC100EP40 is a three
state phase
frequency detector
intended for phase
locked loop applications which require a minimum
amount of phase and frequency difference at lock. Advanced design
significantly reduces the dead zone of the detector. For proper
operation, the input edge rate of the R and V inputs should be less than
5 ns. The device is designed to work with a 3.3 V / 5 V power supply.
When Reference (R) and Feedback (FB) inputs are unequal in
frequency and/or phase the differential UP (U) and DOWN (D)
outputs will provide pulse streams which when subtracted and
integrated provide an error voltage for control of a VCO.
When Reference (R) and Feedback (FB) inputs are 80 ps or less in
phase difference, the Phase Lock Detect pin will indicate lock by a
high state (V
OH
). The V
TX
(V
TR
, V
TR
, V
TFB
, V
TFB
) pins offer an
internal termination network for 50
shown in Figure 2. An external sinking supply of V
CC
2 V is required
on V
TX
pin(s). If you short the two differential V
TR
and V
TR
(or V
TFB
and V
TFB
) together, you provide a 100 termination resistance that is
compatible with LVDS signal receiver termination. For more
information on termination of logic devices, see AND8020.
The V
BB
pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to V
BB
as a switching reference voltage.
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and V
CC
via a 0.01 F capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V
BB
should be left open.
For more information on Phase Lock Loop operation, refer to
AND8040.
Special considerations are required for differential inputs under No
Signal conditions to prevent instability.
line impedance environment
Features
Maximum Frequency > 2 GHz Typical
Fully Differential
Advanced High Band Output Swing of 400 mV
Theoretical Gain = 1.11
T
rise
97 ps Typical, F
fall
70 ps Typical
The 100 Series Contains Temperature Compensation
PECL Mode Operating Range: V
CC
= 3.0 V to 5.5 V
with V
EE
= 0 V
NECL Mode Operating Range: V
CC
= 0 V
with V
EE
=
3.0 V to
5.5 V
50 Internal Termination Resistor
These are Pb
Free Devices
MARKING
DIAGRAM*
TSSOP
20
DT SUFFIX
CASE 948E
A
L
Y
W
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb
Free Package
20
1
http://onsemi.com
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
100
EP40
ALYW
1
20
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
ORDERING INFORMATION
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