參數(shù)資料
型號(hào)： MC-458DA726
廠商： NEC Corp.
英文描述： 8M-Word By72-BIT Dynamic RAM Module(8M×72位動(dòng)態(tài)RAM模塊)
中文描述： 800萬(wàn)字By72位動(dòng)態(tài)內(nèi)存模塊（8米× 72位動(dòng)態(tài)內(nèi)存模塊）
文件頁(yè)數(shù)： 6/16頁(yè)
文件大小： 158K
代理商： MC-458DA726
Data Sheet M13202EJ3V0DS00
6
MC-458DA726
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
[MC-458DA726F]
Parameter
Symbol
Test condition
MIN.
MAX.
Unit
Notes
Operating current
I
CC1
Burst length
=
1, t
RC
≥
t
RC(MIN.)
,
/CAS latency = 2
-A80
1,020
mA
1
I
O
= 0
mA
-A10
930
/CAS latency = 3
-A80
1,065
-A10
975
Precharge standby current in I
CC2
P
CKE
≤
V
IL(MAX.)
, t
CK
=
15
ns
259
mA
power down mode
I
CC2
PS CKE
≤
V
IL(MAX.)
, t
CK
=
∞
14.5
Precharge standby current in
non power down mode
I
CC2
N CKE
≥
V
IH (MIN.)
, t
CK
=
15
ns, /CS
≥
V
IH (MIN.)
,
Input signals are changed one time during 30
ns.
430
mA
I
CC2
NS CKE
≥
V
IH (MIN.)
, t
CK
=
∞
, Input signals are stable.
54
Active standby current in
I
CC3
P
CKE
≤
V
IL(MAX.)
, t
CK
=
15
ns
295
mA
power down mode
I
CC3
PS CKE
≤
V
IL(MAX.)
, t
CK
=
∞
36
Active standby current in
I
CC3
N CKE
≥
V
IH(MIN.)
, t
CK
=
15
ns, /CS
≥
V
IH(MIN.)
,
475
mA
non power down mode
Input signals are changed one time during 30
ns.
I
CC3
NS CKE
≥
V
IH (MIN.)
, t
CK
=
∞
, Input signals are stable.
90
Operating current
I
CC4
t
CK
≥
t
CK(MIN.)
, I
O
= 0
mA
/CAS latency = 2
-A80
1,245
mA
2
(Burst mode)
-A10
1,020
/CAS latency = 3
-A80
1,425
-A10
1,245
CBR (Auto) refresh current
I
CC5
t
RC
≥
t
RC(MIN.)
/CAS latency = 2
-A80
1,470
mA
3
-A10
1,470
/CAS latency = 3
-A80
1,515
-A10
1,515
Self refresh current
I
CC6
CKE
≤
0.2
V
259
mA
Input leakage current
I
I(L)
V
I
=
0 to 3.6
V,
All other pins not under test =
0 V
–
10
+
10
μ
A
Output leakage current
I
O(L)
D
OUT
is disabled, V
O
=
0 to 3.6
V
–
1.5
+
1.5
μ
A
High level output voltage
V
OH
I
O
=
–
4.0
mA
2.4
V
Low level output voltage
V
OL
I
O
=
+
4. 0
mA
0.4
V
Notes 1.
I
CC1
depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, I
CC1
is measured on condition that addresses are changed only one time during t
CK (MIN.)
.
2
. I
CC4
depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, I
CC4
is measured on condition that addresses are changed only one time during t
CK (MIN.)
.
3.
I
CC5
is measured on condition that addresses are changed only one time during t
CK (MIN.)
.
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