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參數(shù)資料
| 型號： | MC-458DA726 |
| 廠商： | NEC Corp. |
| 英文描述： | 8M-Word By72-BIT Dynamic RAM Module(8M×72位動態(tài)RAM模塊) |
| 中文描述： | 800萬字By72位動態(tài)內(nèi)存模塊（8米× 72位動態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 1/16頁 |
| 文件大小： | 158K |
| 代理商： | MC-458DA726 |
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
1998
DATA SHEET
MOS INTEGRATED CIRCUIT
MC-458DA726
8 M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE
REGISTERED TYPE
Document No.
Date Published March 1999 NS CP(K)
Printed in Japan
M13202EJ3V0DS00 (3rd edition)
The mark
#
shows major revised points.
Description
The MC-458DA726 is a 8,388,608 words by 72 bits synchronous dynamic RAM module on which 9 pieces of 64M
SDRAM:
μ
PD4564841 are assembled.
This module provides high density and large quantities of memory in a small space without utilizing the surface-
mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
Features
8,388,608 words by 72 bits organization (ECC type)
Clock frequency and access time from CLK
Part number
/CAS latency
Clock frequency
Access time from CLK
(MAX.)
(MAX.)
MC-458DA726F-A80
CL = 3
125
MHz
6
ns
CL = 2
100 MHz
6 ns
MC-458DA726F-A10
CL = 3
100 MHz
6 ns
CL = 2
77 MHz
7 ns
MC-458DA726LF-A80
CL = 3
125
MHz
6
ns
CL = 2
100 MHz
6 ns
MC-458DA726LF-A10
CL = 3
100 MHz
6 ns
CL = 2
77 MHz
7 ns
Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
Pulsed interface
Possible to assert random column address in every cycle
Quad internal banks controlled by BA0 and BA1 (Bank Select)
Programmable burst-length (1, 2, 4, 8 and Full Page)
Programmable wrap sequence (Sequential
/
Interleave)
Programmable /CAS latency (2, 3)
Automatic precharge and controlled precharge
CBR (Auto) refresh and self refresh
All DQs have 10
±
10
% of series resistor
Single 3.3
V
±
0.3
V power supply
LVTTL compatible
4,096 refresh cycles/64
ms
Burst termination by Burst Stop command and Precharge command
168-pin dual in-line memory module (Pin pitch = 1.27
mm)
Registered type
Serial PD
PC100 registered DIMM Rev. 1.0 compliant
#
#
#
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