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參數(shù)資料
| 型號： | MC-458CD64S |
| 廠商： | NEC Corp. |
| 英文描述： | Synchronous Dynamic RAM Module(同步動態(tài)RAM 模塊) |
| 中文描述： | 同步動態(tài)隨機(jī)存儲器模塊（同步動態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 204K |
| 代理商： | MC-458CD64S |
6
MC-458CD64S
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
Parameter
Symbol
Test condition
MIN.
MAX.
Unit
Notes
Operating current
I
CC1
Burst length
=
1, t
RC
≥
t
RC(MIN.)
/CAS latency = 2
-A80
460
mA
1
-A10
420
-A10B
380
/CAS latency = 3
-A80
560
-A10
460
-A10B
460
Precharge standby current in
I
CC2
P
CKE
≤
V
IL(MAX.)
, t
CK
=
15
ns
8
mA
power down mode
I
CC2
PS
CKE
≤
V
IL(MAX.)
, t
CK
=
∞
4
Precharge standby current in
non power down mode
I
CC2
N
CKE
≥
V
IH(MIN.)
, t
CK
=
15
ns, /CS
≥
V
IH(MIN.)
,
Input signals are changed one time during 30
ns.
160
mA
I
CC2
NS
CKE
≥
V
IH(MIN.)
, t
CK
=
∞
, Input signals are stable.
48
Active standby current in
I
CC3
P
CKE
≤
V
IL(MAX.)
, t
CK
=
15
ns
40
mA
power down mode
I
CC3
PS
CKE
≤
V
IL(MAX.)
, t
CK
=
∞
32
Active standby current in
non power down mode
I
CC3
N
CKE
≥
V
IH(MIN.)
, t
CK
=
15
ns, /CS
≥
V
IH(MIN.)
,
Input signals are changed one time during 30
ns.
200
mA
I
CC3
NS
CKE
≥
V
IH(MIN.)
, t
CK
=
∞
, Input signals are stable.
80
Operating current
I
CC4
t
CK
≥
t
CK(MIN.)
, I
O
= 0
mA
/CAS latency = 2
-A80
760
mA
2
(Burst mode)
-A10
620
-A10B
540
/CAS latency = 3
-A80
880
-A10
760
-A10B
760
Refresh current
I
CC5
t
RC
≥
t
RC(MIN.)
/CAS latency = 2
-A80
620
mA
3
-A10
620
-A10B
520
/CAS latency = 3
-A80
640
-A10
640
-A10B
560
Self refresh current
I
CC6
CKE
≤
0.2
V
-A
8
mA
-A
L
3.2
Input leakage current
I
I(L)
V
I
=
0 to 3.6
V,
All other pins not under test =
0 V
–
8
+8
μ
A
Output leakage current
I
O(L)
D
OUT
is disabled, V
O
=
0 to 3.6
V
–3
+3
μ
A
High level output voltage
V
OH
I
O
=
–
4.0
mA
2.4
V
Low level output voltage
V
OL
I
O
=
+
4.0
mA
0.4
V
Notes 1.
I
CC1
depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, I
CC1
is measured on condition that addresses are changed only one time during t
CK(MIN.)
.
2
. I
CC4
depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, I
CC4
is measured on condition that addresses are changed only one time during t
CK(MIN.)
.
3.
I
CC5
is measured on condition that addresses are changed only one time during t
CK(MIN.)
.
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