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參數(shù)資料
| 型號(hào)： | MB9AF312LPMC1 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 40 MHz, RISC MICROCONTROLLER, PQFP64 |
| 封裝： | 0.50 MM PITCH, PLASTIC, LQFP-64 |
| 文件頁(yè)數(shù)： | 58/114頁(yè) |
| 文件大小： | 1357K |
| 代理商： | MB9AF312LPMC1 |
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ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
48
11.9
Register Description
11.9.1 MCUSR – MCU Status Register
The MCU status register provides information on which reset source caused an MCU reset.
Bit 7:4: Reserved
These bits are unused bits in the Atmel ATmega48PA/88PA/168PA, and will always read as zero.
Bit 3 – WDRF: Watchdog System Reset Flag
This bit is set if a watchdog system reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.
Bit 2 – BORF: Brown-out Reset Flag
This bit is set if a brown-out reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.
Bit 1 – EXTRF: External Reset Flag
This bit is set if an external reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.
Bit 0 – PORF: Power-on Reset Flag
This bit is set if a power-on reset occurs. The bit is reset only by writing a logic zero to the flag.
To make use of the reset flags to identify a reset condition, the user should read and then reset the MCUSR as early as
possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by
examining the reset flags.
11.9.2 WDTCSR – Watchdog Timer Control Register
Bit 7 – WDIF: Watchdog Interrupt Flag
This bit is set when a time-out occurs in the watchdog timer and the watchdog timer is configured for interrupt. WDIF is
cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, WDIF is cleared by writing a
logic one to the flag. When the I-bit in SREG and WDIE are set, the watchdog time-out interrupt is executed.
Bit 6 – WDIE: Watchdog Interrupt Enable
When this bit is written to one and the I-bit in the status register is set, the watchdog interrupt is enabled. If WDE is cleared in
combination with this setting, the watchdog timer is in interrupt mode, and the corresponding interrupt is executed if time-out
in the watchdog timer occurs. If WDE is set, the watchdog timer is in interrupt and system reset mode.
The first time-out in the watchdog timer will set WDIF. Executing the corresponding interrupt vector will clear WDIE and
WDIF automatically by hardware (the watchdog goes to system reset mode). This is useful for keeping the watchdog timer
security while using the interrupt. To stay in interrupt and system reset mode, WDIE must be set after each interrupt. This
should however not be done within the interrupt service routine itself, as this might compromise the safety-function of the
watchdog system reset mode. If the interrupt is not executed before the next time-out, a system reset will be applied.
Bit
7654321
0
––––
WDRF
BORF
EXTRF
PORF
MCUSR
Read/Write
RRRR
R/W
Initial Value
0000
See Bit Description
Bit
765
43210
WDIF
WDIE
WDP3
WDCE
WDE
WDP2
WDP1
WDP0
WDTCSR
Read/Write
R/W
Initial Value
0
X
0
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