參數(shù)資料
型號: MB9AF312LPMC1
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 40 MHz, RISC MICROCONTROLLER, PQFP64
封裝: 0.50 MM PITCH, PLASTIC, LQFP-64
文件頁數(shù): 52/114頁
文件大?。?/td> 1357K
代理商: MB9AF312LPMC1
ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
42
Figure 11-1. Reset Logic
11.3
Power-on Reset
A power-on reset (POR) pulse is generated by an on-chip detection circuit. The detection level is defined in
Section 29.5 “System and Reset Characteristics” on page 272. The POR is activated whenever VCC is below the detection
level. The POR circuit can be used to trigger the start-up reset, as well as to detect a failure in supply voltage.
A power-on reset (POR) circuit ensures that the device is reset from power-on. reaching the power-on reset threshold
voltage invokes the delay counter, which determines how long the device is kept in RESET after VCC rise. The RESET signal
is activated again, without any delay, when VCC decreases below the detection level.
Figure 11-2. MCU Start-up, RESET Tied to VCC
Power-on Reset
Circuit
Brown-out
Reset Circuit
MCU Status
Register (MCUSR)
Reset Circuit
Pull-up Resistor
BODLEVEL [2..0]
S
Q
R
DATA BUS
CK
SUT[1:0]
CKSEL[3:0]
RSTDISBL
COUNTER
RESET
INTERNAL
RESET
TIMEOUT
SPIKE
FILTER
RESET
VCC
Delay Counters
Watchdog
Timer
Watchdog
Oscillator
Clock
Generator
PORF
BORF
WDRF
EXTRF
V
CC
V
CCRR
RESET
INTERNAL
RESET
TIME-OUT
t
TOUT
V
PORMAX
V
PORMIN
V
RST
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