參數(shù)資料
型號： MB9AF311NPMC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 40 MHz, RISC MICROCONTROLLER, PQFP100
封裝： 0.50 MM PITCH, PLASTIC, LQFP-100
文件頁數(shù)： 59/114頁
文件大?。?/td> 1357K
代理商： MB9AF311NPMC
49
ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
Bit 4 – WDCE: Watchdog Change Enable
This bit is used in timed sequences for changing WDE and prescaler bits. To clear the WDE bit, and/or change the prescaler
bits, WDCE must be set.
Once written to one, hardware will clear WDCE after four clock cycles.
Bit 3 – WDE: Watchdog System Reset Enable
WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is set. To clear WDE, WDRF
must be cleared first. This feature ensures multiple resets during conditions causing failure, and a safe start-up after the
failure.
Bit 5, 2:0 - WDP[3:0]: Watchdog Timer Prescaler 3, 2, 1 and 0
The WDP[3:0] bits determine the watchdog timer prescaling when the watchdog timer is running. The different prescaling
values and their corresponding time-out periods are shown in Table 11-2.
Table 11-1. Watchdog Timer Configuration
WDTON(1)
WDE
WDIE
Mode
Action on Time-out
1
0
Stopped
None
1
0
1
Interrupt Mode
Interrupt
1
0
System Reset Mode
Reset
1
Interrupt and System Reset Mode
Interrupt, then go to System Reset
Mode
0
x
System Reset Mode
Reset
Note:
1.
WDTON fuse set to “0” means programmed and “1” means unprogrammed.
Table 11-2. Watchdog Timer Prescale Select
WDP3
WDP2
WDP1
WDP0
Number of WDT Oscillator Cycles
Typical Time-out at
VCC = 5.0V
0
2K (2048) cycles
16ms
0
1
4K (4096) cycles
32ms
0
1
0
8K (8192) cycles
64ms
0
1
16K (16384) cycles
0.125s
0
1
0
32K (32768) cycles
0.25s
0
1
0
1
64K (65536) cycles
0.5s
0
1
0
128K (131072) cycles
1.0s
0
1
256K (262144) cycles
2.0s
1
0
512K (524288) cycles
4.0s
1
0
1
1024K (1048576) cycles
8.0s
1
0
1
0
Reserved
1
0
1
0
1
0
1
0
1
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