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參數(shù)資料
| 型號(hào)： | MB9AF311NPMC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 40 MHz, RISC MICROCONTROLLER, PQFP100 |
| 封裝： | 0.50 MM PITCH, PLASTIC, LQFP-100 |
| 文件頁(yè)數(shù)： | 110/114頁(yè) |
| 文件大?。?/td> | 1357K |
| 代理商： | MB9AF311NPMC |
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95
ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
15.9.3 TCNT0 – Timer/Counter Register
The Timer/Counter register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter.
Writing to the TCNT0 register blocks (removes) the compare match on the following timer clock. Modifying the counter
(TCNT0) while the counter is running, introduces a risk of missing a compare match between TCNT0 and the OCR0x
registers.
15.9.4 OCR0A – Output Compare Register A
The output compare register A contains an 8-bit value that is continuously compared with the counter value (TCNT0). A
match can be used to generate an output compare interrupt, or to generate a waveform output on the OC0A pin.
15.9.5 OCR0B – Output Compare Register B
The output compare register B contains an 8-bit value that is continuously compared with the counter value (TCNT0). A
match can be used to generate an output compare interrupt, or to generate a waveform output on the OC0B pin.
15.9.6 TIMSK0 – Timer/Counter Interrupt Mask Register
Bits 7:3 – Reserved
These bits are reserved bits in the Atmel ATmega48PA/88PA/168PA and will always read as zero.
Bit 2 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable
When the OCIE0B bit is written to one, and the I-bit in the status register is set, the Timer/Counter compare match B interrupt
is enabled. The corresponding interrupt is executed if a compare match in Timer/Counter occurs, i.e., when the OCF0B bit is
set in the Timer/Counter interrupt flag register – TIFR0.
Bit 1 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable
When the OCIE0A bit is written to one, and the I-bit in the status register is set, the Timer/Counter0 compare match A
interrupt is enabled. The corresponding interrupt is executed if a compare match in Timer/Counter0 occurs, i.e., when the
OCF0A bit is set in the Timer/Counter 0 interrupt flag register – TIFR0.
Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is written to one, and the I-bit in the status register is set, the Timer/Counter0 overflow interrupt is
enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in
the Timer/Counter 0 interrupt flag register – TIFR0.
Bit
7654
3210
TCNT0[7:0]
TCNT0
Read/Write
R/W
Initial Value
0000
Bit
76543
210
OCR0A[7:0]
OCR0A
Read/Write
R/W
Initial Value
00000
000
Bit
765
43210
OCR0B[7:0]
OCR0B
Read/Write
R/W
Initial Value
000
00000
Bit
7
6
5
4
3
2
1
0
–
OCIE0B
OCIE0A
TOIE0
TIMSK0
Read/Write
R
R/W
Initial Value
0
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