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參數(shù)資料
| 型號： | MB91V301CR-ESE1 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 68 MHz, RISC MICROCONTROLLER, CPGA179 |
| 封裝： | CERAMIC, PGA-179 |
| 文件頁數(shù)： | 64/139頁 |
| 文件大?。?/td> | 1482K |
| 代理商： | MB91V301CR-ESE1 |
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MB91301 Series
30
R15 (General purpose register)
When any of the following instructions is executed, the SSP* or USP* value is not used as R15, resulting in an
incorrect value written to memory.
* : R15 is a virtual register. When a program attempts to access R15, the SSP or USP is accessed depending
on the status of the “S” flag as an SP flag. When coding the above ten instructions using an assembler,
specify a general-purpose register other than R15.
RETI instruction
Please do not neither control register of the instruction cache nor the data access to RAM of the instruction
cache immediately before the instruction of RETI.
Notes on the PS register
Since some instructions manipulate the PS register earlier, the following exceptions may cause the interrupt
handler to break or the PS flag to update its display setting when the debugger is being used. As the microcon-
troller is designed to carry out reprocessing correctly upon returning from such an EIT event, it performs oper-
ations before and after the EIT as specified in either case.
The following operations may be performed when the instruction immediately followed by a DIVOU/DIVOS
instruction is (a) halted by a user interrupt or NMI, (b) single-stepped, or (c) breaks in response to a data
event or emulator menu:
(1) D0 and D1 flags are updated earlier.
(2) The EIT handler (user interrupt/NMI or emulator) is executed.
(3) Upon returning from the EIT, the DIVOU/DIVOS instruction is executed and the D0 and D1 flags are
updated to the same values as those in (1) above.
The following operations are performed when the ORCCR/STILM/MOV Ri and PS instructions are executed
to enable interruptions when a user interrupt or NMI trigger event has occurred.
(1) The PS register is updated earlier.
(2) The EIT handler (user interrupt/NMI or emulator) is executed.
(3) Upon returning from the EIT, the above instructions are executed and the PS register is updated to the
same value as that in (1) above.
A/D converter
When the device is turned on or returns from a reset or stop, it takes time for the external capacitor to be charged,
requiring the A/D converter to wait for at least 10 ms.
Watchdog timer
The watchdog timer function of this model monitors that a program delays a reset within a certain period of time
and resets the CPU if the program fails to delay it, for example, because the program runs out of control. Once
the watchdog timer function is enabled, therefore, the watchdog timer countinues to operate until a reset takes
place.
An exception, for example during stop, sleep and DMA transfer modes, is the automatic delaying of a reset under
a condition in which the CPU stops program execution.
Note, however, that a watchdog reset may not occur in the above state caused when the system runs out of
control. If this is the case, use the external INIT pin to cause a reset (INIT) .
AND
R15, @Ri
ANDH
R15, @Ri
ANDB
R15, @Ri
OR
R15, @Ri
ORH
R15, @Ri
ORB
R15, @Ri
EOR
R15, @Ri
EORH
R15, @Ri
EORB
R15, @Ri
XCHB
@Rj, R15
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