參數(shù)資料
型號： MB90F395HPMT
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 24 MHz, MICROCONTROLLER, PQFP120
封裝： PLASTIC, LQFP-120
文件頁數(shù)： 46/66頁
文件大小： 917K
代理商： MB90F395HPMT
MB90390 Series
50
(4) UART0/1/2 and Serial I/O Timing
(TA
= 40 °C to +85 °C, VCC = 3.5 V to 5.5 V, VSS = 0 V)
Notes :
Above rating is the case of CLK synchronized mode.
CL is load capacity value of pins when testing.
tCP is the machine clock cycle time. Refer to “ (1) Clock timing”.
Parameter
Sym-
bol
Pin
Condition
Value
Unit
Re-
marks
Min
Max
Serial clock cycle time
tSCYC
SCK0 to SCK2, SCK4
Internal clock
operation output
pins are
CL
= 80 pF + 1 TTL.
8 tCP
ns
SCK
↓ → SOT delay time
tSLOVI
SCK0 to SCK2, SCK4,
SOT0 to SOT2, SOT4
80
+80
ns
Valid SIN
→ SCK ↑
tIVSHI
SCK0 to SCK2, SCK4,
SIN0 to SIN2, SIN4
100
ns
SCK
↑ → Valid SIN hold time tSHIXI
SCK0 to SCK2, SCK4,
SIN0 to SIN2, SIN4
60
ns
Serial clock “H” pulse width
tSHSL
SCK0 to SCK2, SCK4
External clock
operation output
pins are
CL
= 80 pF + 1 TTL.
4 tCP
ns
Serial clock “L” pulse width
tSLSH
SCK0 to SCK2, SCK4
4 tCP
ns
SCK
↓ → SOT delay time
tSLOVE
SCK0 to SCK2, SCK4,
SOT0 to SOT2, SOT4
150
ns
Valid SIN
→ SCK ↑
tIVSHE
SCK0 to SCK2, SCK4,
SIN0 to SIN2, SIN4
60
ns
SCK
↑ → Valid SIN hold time tSHIXE
SCK0 to SCK2, SCK4,
SIN0 to SIN2, SIN4
60
ns
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