參數(shù)資料
型號(hào)： MB90246APFV
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： 16-bit Proprietary Microcontroller
中文描述： 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP100
封裝： PLASTIC, LQFP-100
文件頁數(shù)： 94/100頁
文件大?。?/td> 1956K
代理商： MB90246APFV
94
MB90246A Series
Table 22 Miscellaneous Control Types (Byte, Word, Long) [36 Instructions]
Note: For (a) and (c), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5 Correction
Values for Number of Cycles for Calculating Actual Number of Cycles.”
*1: PCB, ADB, SSB, USB, and SPB : 1 state
DTB
DPR
*2: 3 + 4
×
(number of POPs)
: 2 states
: 3 states
Mnemonic
#
~
B
Operation
LH AH
I
S
T
N
Z
V
C RMW
PUSHW A
PUSHW AH
PUSHW PS
PUSHW rlst
POPW
POPW
POPW
POPW
A
AH
PS
rlst
JCTX
@A
AND
OR
CCR, #imm8
CCR, #imm8
MOV
MOV
RP, #imm8
ILM, #imm8
MOVEA RWi, ear
MOVEA RWi, eam
MOVEA A, ear
MOVEA A, eam
ADDSP #imm8
ADDSP #imm16
MOV
MOV
MOV
A, brgl
brg2, A
brg2, #imm8
NOP
ADB
DTB
PCB
SPB
NCC
CMR
MOVW SPCU, #imm16
MOVW SPCL, #imm16
SETSPC
CLRSPC
BTSCN A
BTSCNS
A
BTSCND
A
1
1
1
2
1
1
1
2
1
2
2
2
2
2
2 +
2
2 +
2
3
2
2
3
1
1
1
1
1
1
1
4
4
2
2
2
2
2
3
3
3
*3
3
3
3
*2
9
3
3
2
2
3
2 + (a)
2
1 + (a)
3
3
*1
1
2
1
1
1
1
1
1
1
2
2
2
2
*5
*6
*7
(c)
(c)
(c)
*4
(c)
(c)
(c)
*4
6
×
(c)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
word (SP)
←
(SP) – 2, ((SP))
←
(A)
word (SP)
←
(SP) – 2, ((SP))
←
(AH)
word (SP)
←
(SP) – 2, ((SP))
←
(PS)
(PS)
←
(PS) – 2n, ((SP))
←
(rlst)
word (A)
←
((SP)), (SP)
← (
SP) + 2
word (AH)
←
((SP)), (SP)
← (
SP) + 2
word (PS)
←
((SP)), (SP)
← (
SP) + 2
(rlst)
←
((SP)), (SP)
←
(SP) + 2n
Context switch instruction
byte (CCR)
←
(CCR) and imm8
byte (CCR)
←
(CCR) or imm8
byte (RP)
←
imm8
byte (ILM)
←
imm8
word (RWi)
←
ear
word (RWi)
←
eam
word(A)
←
ear
word (A)
←
eam
word (SP)
←
(SP) + ext (imm8)
word (SP)
←
(SP) + imm16
byte (A)
←
(brgl)
byte (brg2)
←
(A)
byte (brg2)
←
imm8
No operation
Prefix code for accessing AD space
Prefix code for accessing DT space
Prefix code for accessing PC space
Prefix code for accessing SP space
Prefix code for no change in flag
Prefix for common register bank
word (SPCU)
←
(imm16)
word (SPCL)
←
(imm16)
Enables stack check operation.
Disables stack check operation.
Bit position of 1 in byte (A) from word (A)
Bit position (
×
2) of 1 in byte (A) from word
(A)
Bit position (
×
4) of 1 in byte (A) from word
(A)
–
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Z
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Z
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Z
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