參數(shù)資料
型號(hào)： MB90246APFV
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： 16-bit Proprietary Microcontroller
中文描述： 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP100
封裝： PLASTIC, LQFP-100
文件頁(yè)數(shù)： 65/100頁(yè)
文件大?。?/td> 1956K
代理商： MB90246APFV
65
MB90246A Series
(3) Bus Read Timing
(AV
CC
= V
CC
= 2.7 V to 5.5 V, AV
SS
= V
SS
= 0.0 V, T
A
= –40
°
C to +85
°
C)
N: Stands for the number of wait cycles. With no wait, N is set at “0”. (The number of wait cycles depends on an
automatic wait and external RDY.)
* :For t
CYC
(cycle time (machine cycle)), see paragraph (4), “Clock output timing.”
Parameter
Symbol
Pin name
Condition
Value
Unit
Remarks
Min.
Max.
Effective address
→
RD
↓
time
Effective address
→
effective data input
t
AVRL
A00 to A23
V
CC
= 5.0 V ±10%
1 t
CYC
*/2 – 20
—
ns
t
AVDV
D15 to D00
—
(N + 1.5)
×
1 t
CYC
* – 40
ns
RD pulse width
t
RLRH
RD
—
(N + 1)
×
1 t
CYC
* – 25
—
ns
RD
↓
→
effective data
input
RD
↑
→
data hold time t
RHDX
RD
↑
→
address
effective time
Effective address
→
CLK
↑
time
RD
↓
→
CLK
↑
time
t
RLDV
D15 to D00
V
CC
= 5.0 V ±10%
—
(N + 1)
×
1 t
CYC*
* – 30
—
ns
D15 to D00
—
0
ns
t
RHAX
A00 to A23
1 t
CYC
*/2 – 20
—
ns
t
AVCH
CLK,
A00 to A23
RD, CLK
1 t
CYC
*/2 – 25
—
ns
t
RLCL
1 t
CYC
*/2 – 25
—
ns
CLK
RD
A00 to A23
D00 to D15
t
AVCH
t
RLCL
2.4 V
0.8 V
0.8 V
2.4 V
2.4 V
0.8 V
t
AVRL
t
AVDV
t
RLDV
t
RHAX
t
RHDX
t
RLRH
0.8 V
2.4 V
0.8 V
2.2 V
0.8 V
2.2 V
0.8 V
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