參數(shù)資料
型號(hào)： MB90246APFV
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： 16-bit Proprietary Microcontroller
中文描述： 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP100
封裝： PLASTIC, LQFP-100
文件頁數(shù)： 68/100頁
文件大小： 1956K
代理商： MB90246APFV
68
MB90246A Series
RD/WRH/WRL signal standards
(AV
CC
= V
CC
= 4.5 V to 5.5 V, AV
SS
= V
SS
= 0.0 V, T
A
= –30
°
C to +70
°
C)
N: Stands for the number of wait cycles. With no wait, N is set at “0”. (The number of wait cycles depends on an
automatic wait and external RDY.)
m: Stands for the number of RDY wait cycles. With no wait, m is set at “0”.
*1: Use the automatic ready function when the setup time is not sufficient.
*2: If the pulse width has exceeded the maximum value, the wait period may be extended beyond the specified
number of cycles by one cycle.
*3: For t
CYC
(cycle time (machine cycle)), see paragraph (4), “Clock output timing.”
Parameter
Symbol
Pin name
Condition
Value
Unit Remarks
Min.
Max.
RD/WRH/WRL
↓ →
RDY
↓
time
t
RYHS
RD/WRH/
WRL,
RDY
—
0
N
×
1 t
CYC
*
3
+ 15*
1
ns
RDY pulse width
t
RYPW
RDY
V
CC
= 5.0 V
±
10%
1/2 t
CYC
*
3
+ 20
(m + 1)
×
1
t
CYC
*
2,
*
3
ns
RDY
↑ →
RD
↑
t
RHDV
RD/WRH/
WRL,
RDY
—
1 t
CYC
*
3
– 15
2 t
CYC
*
3
– 25
ns
RD/WRH/WRL
RDY
(wait not inserted)
RDY
(wait inserted)
A00 to A23
t
RHDV
0.8 V
t
RYHS
2.2 V
0.8 V
2.4 V
Ready input timing (RD/WRH/WRL signal standards)
2.2 V
t
RYPW
2.2 V
0.8 V
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