
vi
3.7.5
Diagram for State Transition in Standby Mode .............................................................................. 74
3.7.6
Notes on Standby Mode ................................................................................................................ 76
3.8
Memory Access Mode ........................................................................................................................ 78
CHAPTER 4
I/O PORTS .................................................................................................. 81
4.1
Overview of I/O Ports .......................................................................................................................... 82
4.2
Port 0 .................................................................................................................................................. 84
4.2.1
Registers of Port 0 (PDR0, DDR0, PUL0) .................................................................................... 88
4.2.2
Explanation of Operations of Port 0 Functions .............................................................................. 91
4.3
Port 3 .................................................................................................................................................. 93
4.3.1
Registers of Port 3 (PDR3, DDR3, PUL3) ..................................................................................... 96
4.3.2
Explanation of Operations of Port 3 Functions .............................................................................. 98
4.4
Port 4 ................................................................................................................................................ 100
4.4.1
Registers of Port 4 (PDR4) .......................................................................................................... 102
4.4.2
Explanation of Operations of Port 4 Functions ............................................................................ 104
4.5
Port 5 ................................................................................................................................................ 105
4.5.1
Registers of Port 5 (PDR5, DDR5, PUL5) ................................................................................... 107
4.5.2
Explanation of Operations of Port 5 Functions ............................................................................ 110
4.6
Program Example for I/O Port ........................................................................................................... 112
CHAPTER 5
TIMEBASE TIMERS ................................................................................. 115
5.1
Overview of Timebase Timer ............................................................................................................ 116
5.2
Configuration of Timebase Timer ...................................................................................................... 118
5.3
Timebase Timer Control Register (TBTC) ........................................................................................ 120
5.4
Interrupt of Timebase Timer .............................................................................................................. 122
5.5
Explanation of Operations of Timebase Timer Functions ................................................................. 123
5.6
Notes on Using Timebase Timer ...................................................................................................... 125
5.7
Program Example for Timebase Timer ............................................................................................. 126
CHAPTER 6
WATCHDOG TIMERS .............................................................................. 129
6.1
Overview of Watchdog Timer ............................................................................................................ 130
6.2
Configuration of Watchdog Timer ..................................................................................................... 131
6.3
Watchdog Control Register (WDTC) ................................................................................................. 132
6.4
Explanation of Operations of Watchdog Timer Functions ................................................................. 133
6.5
Notes on Using Watchdog Timer ...................................................................................................... 135
6.6
Program Example for Watchdog Timer ............................................................................................ 136
CHAPTER 7
8-BIT PWM TIMERS ................................................................................. 137
7.1
Overview of 8-bit PWM Timers ......................................................................................................... 138
7.2
Configuration of 8-bit PWM Timers ................................................................................................... 141
7.3
Pin of 8-bit PWM Timers ................................................................................................................... 143
7.4
Registers of 8-bit PWM Timers ......................................................................................................... 144
7.4.1
PWM Control Register (CNTR) .................................................................................................... 145
7.4.2
PWM Compare Register (COMR) ................................................................................................ 147
7.5
Interrupt of 8-bit PWM Timers ........................................................................................................... 149
7.6
Explanation of Operations of the Interval Timer Functions ............................................................... 150
7.7
Explanation of Operations of the 8-bit PWM Timer Functions .......................................................... 152
7.8
States in Each Mode During Operation ............................................................................................ 154