參數(shù)資料
型號(hào)： MB81ES653225-12
廠商： Fujitsu Limited
英文描述： Consumer/Embedded Application Specific Memory for SiP
中文描述： 消費(fèi)/嵌入式SIP應(yīng)用程序特定的內(nèi)存
文件頁(yè)數(shù)： 14/44頁(yè)
文件大?。?/td> 485K
代理商： MB81ES653225-12
MB81ES653225-12/-12L
14
■
FUNCTIONAL DESCRIPTION
1.
SDR I/F FCRAM BASIC FUNCTION
Three major differences between this SDR I/F FCRAMs and conventional DRAMs are : synchronized operation,
burst mode, and mode register.
The synchronized operation is the fundamental difference. An SDR I/F FCRAM uses a clock input for the
synchronization, where the DRAM is basically asynchronous memory although it has been using two clocks,
RAS and CAS. Each operation of DRAM is determined by their timing phase differences while each operation
of SDR I/F FCRAM is determined by commands and all operations are referenced to a positive clock edge.
The burst mode is a very high speed access mode utilizing an internal column address generator. Once a column
addresses for the first access is set, following addresses are automatically generated by the internal column
address counter.
The mode register is to justify the SDR I/F FCRAM operation and function into desired system conditions. Refer
to “
■
MODE REGISTER TABLE”.
2.
FCRAM
TM
The MB81ES653225 utilizes FCRAM core technology. The FCRAM is an acronym of Fast Cycle Random Access
Memory and provides very fast random cycle time, low latency and low power consumption than regular DRAMs.
3.
CLOCK INPUT (CLK) and CLOCK ENABLE (CKE)
All input and output signals of SDR I/F FCRAM use register type buffers. A CLK is used as a trigger for the
register and internal burst counter increment. All inputs are latched by a positive edge of CLK. All outputs are
validated by the CLK. CKE is a high active clock enable signal. When CKE
=
Low is latched at a clock input during
active cycle, the next clock will be internally masked. During idle state (all banks have been precharged) , the
Power Down mode (standby) is entered with CKE
=
Low and this will make low standby current. The standby
current of the Deep Power Down mode is lower than that of the Power Down mode. This mode is entered with
CKE
=
Low, RAS
=
CAS
=
High and WE
=
Low.
4.
CHIP SELECT (CS)
CS enables all commands inputs, RAS, CAS, and WE, and address input. When CS is High, command signals
are negated but internal operation such as burst cycle will not be suspended. If such a control isn’t needed, CS
can be tied to ground level.
5.
COMMAND INPUT (RAS, CAS and WE)
Unlike a conventional DRAM, RAS, CAS, and WE do not directly imply SDR I/F FCRAM operation, such as Row
address strobe by RAS. Instead, each combination of RAS, CAS, and WE input in conjunction with CS input at
a rising edge of the CLK determines SDR I/F FCRAM operation. Refer to “1. COMMAND TRUTH TABLE” in
section “
■
FUNCTIONAL TRUTH TABLE.”
6.
ADDRESS INPUT (A
14
to A
0
)
Address input selects an arbitrary location of a total of 1,048,576 words of each memory cell matrix. Address
field is defined for selected page length by the Programmable Page Length mode : 128 page length
=
A
12
to A
0
,
64 page length
=
A
13
to A
0
, 32 page length
=
A
14
to A
0
. A total of twenty address input signals are required to
decode such a matrix. SDR I/F FCRAM adopts an address multiplexer in order to reduce the pin count of the
address line. At a Bank Active command (ACTV) , Row addresses are initially latched and the remainder of
Column addresses are then latched by a Column address strobe command of either a Read command (READ
or READA) or Write command (WRIT or WRITA) .
相關(guān)PDF資料
PDF描述
MB81ES653225-12L Consumer/Embedded Application Specific Memory for SiP
MB81N643289 DRILL BIT HIGH SPEED STEEL .021,1
MB84VA2102 16M (x16) FLASH MEMORY & 2M (x 8) STATIC RAM
MB84VA2102-10 16M (x16) FLASH MEMORY & 2M (x 8) STATIC RAM
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MB81ES653225-12L 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Consumer/Embedded Application Specific Memory for SiP
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