Dual I2S Stereo Audio Codec _______________" />
參數(shù)資料
型號: MAX9880AEWM+T
廠商: Maxim Integrated Products
文件頁數(shù): 51/70頁
文件大?。?/td> 0K
描述: IC CODEC AUDIO STEREO 48WLP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
類型: 立體聲音頻
數(shù)據(jù)接口: I²C,I²S,串行,SPI?
ADC / DAC 數(shù)量: 2 / 2
三角積分調(diào)變:
動態(tài)范圍,標(biāo)準(zhǔn) ADC / DAC (db): 82 / 96
電壓 - 電源,模擬: 1.65 V ~ 1.95 V
電壓 - 電源,數(shù)字: 1.65 V ~ 1.95 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-WFBGA,WLCSP
供應(yīng)商設(shè)備封裝: 48-WLP(2.70x3.50)
包裝: 帶卷 (TR)
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
______________________________________________________________________________________
55
BITS
FUNCTION
Headphone Amplifier Mode
HPMODE
MODE
000
Stereo differential
001
Mono (left) differential
010
Stereo capacitorless
011
Mono (left) capacitorless
100
Stereo single-ended (clickless)
101
Mono (left) single-ended (clickless)
110
Stereo single-ended (fast turn-on)
111
Mono (left) single-ended (fast turn-on)
HPMODE
Note: In mono operation, the right amplifier is disabled.
JDETEN
Jack-Detection Enable
SHDN = 0: Sleep Mode. Enables pullups on JACKSNS/AUX to detect jack insertion.
SHDN = 1: Normal Mode. Enables the comparator circuitry on JACKSNS/AUX to detect voltage changes.
Note: AUXEN must be set to 0 for jack detection to function.
JDWK
Jack-Sense Weak Pullup. Enables an internal pullup. Set JDWK = 1 to enable an internal 4A current
source. Set JDWK = 0 for external pullup.
Jack Detect Debounce. Configures the JDET debounce time for changes to JKSNS[1:0] according to
information below.
JDEB
DEBOUNCE TIME (ms)
00
25
01
50
10
100
JDEB
11
200
Table 24. Mode Configuration Register (continued)
Power Management
The MAX9880A includes complete power management
control to minimize power usage. The DAC and both
ADCs can be independently enabled so that only the
required circuitry is active.
Revision Code
The MAX9880A includes a revision code to allow easy
identification of the device revision. Revision code at
register address 0xFF is not accessible through the SPI
interface and so the revision code is accessible
through SPI at an additional address of 0x214. The cur-
rent revision code is 0x42.
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