Dual I2S Stereo Audio Codec 40 ____________" />
參數(shù)資料
型號： MAX9880AEWM+T
廠商： Maxim Integrated Products
文件頁數(shù)： 35/70頁
文件大小： 0K
描述： IC CODEC AUDIO STEREO 48WLP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
類型： 立體聲音頻
數(shù)據(jù)接口： I²C，I²S，串行，SPI?
ADC / DAC 數(shù)量： 2 / 2
三角積分調(diào)變： 是
動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： 82 / 96
電壓 - 電源，模擬： 1.65 V ~ 1.95 V
電壓 - 電源，數(shù)字： 1.65 V ~ 1.95 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-WFBGA，WLCSP
供應(yīng)商設(shè)備封裝： 48-WLP（2.70x3.50）
包裝： 帶卷 (TR)
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
40
______________________________________________________________________________________
CODE
FILTER TYPE
VALID SAMPLE
RATE (kHz)
HIGHPASS CORNER FREQUENCY
217Hz NOTCH
0x0
Disabled
0x1
Elliptical
16
256Hz
Yes
0x2
Butterworth
16
500Hz
No
0x3
Elliptical
8
256Hz
Yes
0x4
Butterworth
8
500Hz
No
0x5
Butterworth
8 to 24
fS/240
No
0x6 to 0x7
Reserved
Table 10. IIR Highpass Digital Filters
Digital Filtering
The MAX9880A incorporates both IIR (voice) and FIR
(audio) digital filters to accomodate a wide range of
audio sources. The IIR fiilters provide over 70dB of
stopband attenuation as well as selectable highpass fil-
ters. The FIR filters provide low power consumption and
are linear phase to maintain stereo imaging.
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
REGISTER
ADDRESS
(SEE NOTE)
DIGITAL FILTERING
Codec Filters
MODE
AVFLT
DCB
DVFLT
0x11
BITS
FUNCTION
MODE
Digital Audio Filter Mode. Selects the filtering mode for the DAI1 DAC and ADC signal paths.
0 = IIR voice filters
1 = FIR audio filters
AVFLT
ADC Digital Audio Filter. Configures the highpass filters for the DAI1 signal path.
MODE = 0
Select the desired digital filter response from Table 10. See the frequency response graphs in the Typical
Operating Characteristics section for details on each filter.
MODE = 1
0x0 = DC-blocking filter disabled.
0x1 = DC-blocking filter enabled.
DCB
1 = DC-blocking filter for DAI2 enabled.
0 = DC-blocking filter for DAI2 disabled.
DVFLT
DAC Digital Audio Filter. Configures the highpass filters for the DAI1 signal path.
MODE = 0
Select the desired digital filter response from Table 10. See the frequency response graphs in the Typical
Operating Characteristics section for details on each filter.
MODE = 1
0x0 = DC-blocking filter disabled.
0x1 = DC-blocking filter enabled.
Table 9. Digital Filtering Register
Note: Register addresses listed are for I2C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
accessible through SPI.
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