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參數(shù)資料
| 型號： | MAX9880AEWM+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 24/70頁 |
| 文件大小： | 0K |
| 描述： | IC CODEC AUDIO STEREO 48WLP |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 類型： | 立體聲音頻 |
| 數(shù)據(jù)接口： | I²C，I²S，串行，SPI? |
| ADC / DAC 數(shù)量： | 2 / 2 |
| 三角積分調(diào)變： | 是 |
| 動態(tài)范圍，標準 ADC / DAC (db)： | 82 / 96 |
| 電壓 - 電源，模擬： | 1.65 V ~ 1.95 V |
| 電壓 - 電源，數(shù)字： | 1.65 V ~ 1.95 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-WFBGA，WLCSP |
| 供應商設備封裝： | 48-WLP（2.70x3.50） |
| 包裝： | 帶卷 (TR) |
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MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
30
______________________________________________________________________________________
Hardware Interrupts
Hardware interrupts are reported on the open-drain IRQ
pin. When an interrupt occurs, IRQ remains low until the
interrupt is serviced by reading the status register 0x00.
If a flag is set, it is reported as a hardware interrupt only
if the corresponding interrupt enable is set. Each bit
enables interrupts for the status flag in the respective
bit location in register 0x00.
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
REGISTER
ADDRESS
(SEE NOTE)
Interrupt Enable
ICLD
ISLD
IULK
0
0*
IJDET
0
0x04
Table 4. Interrupt Enable
*
Reserved.
Grayed boxes = Not used.
Note: Register addresses listed are for I2C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
accessible through SPI.
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
REGISTER
ADDRESS
(SEE NOTE)
SYSTEM CLOCK CONTROL
System Clock
0
PSCLK
FREQ1
0x05
DAI1 CLOCK CONTROL
Stereo Audio Clock Control High
PLL1
NI1[14:8]
0x06
Stereo Audio Clock Control Low
NI1[7:1]
RLK1/NI1[0]
0x07
DAI2 CLOCK CONTROL
Stereo Audio Clock Control High
PLL2
NI2[14:8]
0x0B
Stereo Audio Clock Control Low
NI2[7:1]
RLK2/NI2[0]
0x0C
Table 5. System and Audio Clock Registers
Grayed boxes = Not used.
Note: Register addresses listed are for I2C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
accessible through SPI.
Clock Control
The MAX9880A can work with a master clock (MCLK)
supplied from any system clock within the 10MHz to
60MHz range. Internally the MAX9880A requires a
10MHz to 20MHz clock. A prescaler divides MCLK by
1, 2, or 4 to create the internal clock (PCLK). PCLK is
used to clock all portions of the MAX9880A.
The MAX9880A can support any sample rate from 8kHz
to 48kHz for the digital audio path DAI1 (DAC and
ADC) and 8kHz to 96kHz for the DAI2 (high-fidelity
DAC path), including all common sample rates (8kHz,
16kHz, 24kHz, 32kHz, 44.1kHz, 48kHz, 96kHz). To
accommodate a wide range of system architectures,
the MAX9880A supports three main clocking modes:
Normal mode: This mode uses a 15-bit clock
divider coefficient to set the sample rate relative to
the prescaled MCLK input (PCLK). This allows high
flexibility in both the MCLK and LRCLK frequencies
and can be used in either master or slave mode.
Exact integer mode: Common MCLK frequencies
(12MHz, 13MHz, 16MHz, and 19.2MHz) can be pro-
grammed to operate in exact integer mode for both
8kHz and 16kHz sample rates. In these modes, the
MCLK and LRCLK rates are selected by using the
FREQ1 bits instead of the NI high, NI low, and PLL con-
trol bits.
PLL mode: When operating in slave mode, a PLL
can be enabled to lock onto externally generated
LRCLK signals that are not integer related to PCLK.
Prior to enabling the interface, program NI to the
nearest desired ratio and set the NI[0] = 1 to enable
the PLL’s rapid lock mode. If NI[0] = 0, then NI is
ignored and PLL lock time is slower.
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參數(shù)描述 |
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| MAX9880ETM+ | 制造商:Maxim Integrated Products 功能描述:AUDIO CODEC - Rail/Tube |
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| MAX9880EWM+T | 制造商:Maxim from Components Direct 功能描述:THE MAXIM MAX9880EWM+T IS AN AUDIO CODEC CONVERTER. - Tape and Reel 制造商:Maxim 功能描述:Maxim MAX9880EWM+T, Audio CODEC Converter Dual I2S 1.8V 48-bump WLP |
| MAX9888EVKIT+ | 功能描述:音頻 IC 開發(fā)工具 MAX9888 Eval Kit RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V |
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