參數(shù)資料
型號(hào): MAX9879ERV+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 18/32頁(yè)
文件大?。?/td> 0K
描述: IC AUDIO SUBSYSTEM 30-UCSP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
系列: DirectDrive®
類型: D 類
輸出類型: 2-通道(立體聲)帶立體聲耳機(jī)
在某負(fù)載時(shí)最大輸出功率 x 通道數(shù)量: 715mW x 2 @ 8 歐姆; 58mW x 2 @ 16 歐姆
電源電壓: 2.7 V ~ 5.5 V
特點(diǎn): 消除爆音,差分輸入,I²C,靜音,短路和熱保護(hù),關(guān)機(jī),音量控制
安裝類型: 表面貼裝
供應(yīng)商設(shè)備封裝: 30-UCSP(5x6)
封裝/外殼: 30-WFBGA,CSPBGA
包裝: 帶卷 (TR)
MAX9879
Stereo Class D Audio Subsystem
with DirectDrive Headphone Amplifier
25
Maxim Integrated
1
SCL
START
CONDITION
SDA
28
9
CLOCK PULSE FOR
ACKNOWLEDGMENT
ACKNOWLEDGE
NOT ACKNOWLEDGE
Figure 8. Acknowledge
A START (S) condition from the master signals the
beginning of a transmission to the MAX9879. The mas-
ter terminates transmission, and frees the bus, by issu-
ing a STOP condition. The bus remains active if a
REPEATED START (Sr) condition is generated instead of
a STOP condition.
Early STOP Conditions
The MAX9879 recognizes a STOP (P) condition at any
point during data transmission except if the STOP (P)
condition occurs in the same high pulse as a START (S)
condition. For proper operation, do not send a STOP
(P) condition during the same SCL high pulse as the
START (S) condition.
Slave Address
The MAX9879 is preprogrammed with a slave address
of 1001101R/(W). The address is defined as the seven
most significant bits (MSBs) followed by the Read/Write
bit. Setting the Read/Write bit to 1 configures the
MAX9879 for read mode. Setting the Read/Write bit to 0
configures the MAX9879 for write mode. The address is
the first byte of information sent to the MAX9879 after
the START (S) condition.
Acknowledge
The acknowledge bit (ACK) is a clocked 9th bit that the
MAX9879 uses to handshake receipt each byte of data
when in write mode (see Figure 8). The MAX9879 pulls
down SDA during the entire master-generated 9th
clock pulse if the previous byte is successfully
received. Monitoring ACK allows for detection of unsuc-
cessful data transfers. An unsuccessful data transfer
occurs if a receiving device is busy or if a system fault
has occurred. In the event of an unsuccessful data
transfer, the bus master may retry communication.
The master pulls down SDA during the ninth clock
cycle to acknowledge receipt of data when the
MAX9879 is in read mode. An acknowledge is sent by
the master after each read byte to allow data transfer to
continue. A not acknowledge is sent when the master
reads the final byte of data from the MAX9879, followed
by a STOP (P) condition.
Write Data Format
A write to the MAX9879 includes transmission of a
START (S) condition, the slave address with the R/W bit
set to 0, one byte of data to configure the internal regis-
ter address pointer, one or more bytes of data, and a
STOP (P) condition. Figure 9 illustrates the proper
frame format for writing one byte of data to the
SCL
SDA
SSr
P
Figure 7. START (S), STOP (P), and REPEATED START (Sr) Conditions
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