參數(shù)資料
型號: MAX9879ERV+T
廠商: Maxim Integrated Products
文件頁數(shù): 17/32頁
文件大小: 0K
描述: IC AUDIO SUBSYSTEM 30-UCSP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
系列: DirectDrive®
類型: D 類
輸出類型: 2-通道(立體聲)帶立體聲耳機(jī)
在某負(fù)載時(shí)最大輸出功率 x 通道數(shù)量: 715mW x 2 @ 8 歐姆; 58mW x 2 @ 16 歐姆
電源電壓: 2.7 V ~ 5.5 V
特點(diǎn): 消除爆音,差分輸入,I²C,靜音,短路和熱保護(hù),關(guān)機(jī),音量控制
安裝類型: 表面貼裝
供應(yīng)商設(shè)備封裝: 30-UCSP(5x6)
封裝/外殼: 30-WFBGA,CSPBGA
包裝: 帶卷 (TR)
MAX9879
Stereo Class D Audio Subsystem
with DirectDrive Headphone Amplifier
24
Maxim Integrated
Bypass Mode (BYPASS)
1 = MAX9879 bypass switches are closed and the
Class D amplifier is disabled.
0 = Bypass mode disabled.
This mode does not control headphone operation.
Output Mode Control Register
Speaker/Headphone Output Mode
(_SPKEN/HPEN)
The MAX9879 features independent enables and input
selection for each speaker amplifier and the headphone
amplifier. See Table 6 for a detailed description of the
available modes. If the right speaker amplifier is disabled,
the stereo signals are automatically summed to mono for
the left output and vice-versa.
I2C Interface Specification
The MAX9879 features an I2C/SMBus-compatible,
2-wire serial interface consisting of a serial-data line
(SDA) and a serial-clock line (SCL). SDA and SCL facil-
itate communication between the MAX9879 and the
master at clock rates up to 400kHz. Figure 6 shows the
2-wire interface timing diagram. The master generates
SCL and initiates data transfer on the bus. The master
device writes data to the MAX9879 by transmitting the
proper slave address followed by the register address
and then the data word. Each transmit sequence is
framed by a START (S) or REPEATED START (Sr) con-
dition and a STOP (P) condition. Each word transmitted
to the MAX9879 is 8 bits long and is followed by an
acknowledge clock pulse. A master reading data from
the MAX9879 transmits the proper slave address fol-
lowed by a series of nine SCL pulses. The MAX9879
transmits data on SDA in sync with the master-generat-
ed SCL pulses. The master acknowledges receipt of
each byte of data. Each read sequence is framed by a
START (S) or REPEATED START (Sr) condition, a not
acknowledge, and a STOP (P) condition. SDA operates
as both an input and an open-drain output. A pullup
resistor, typically greater than 500
Ω, is required on
SDA. SCL operates only as an input. A pullup resistor,
typically greater than 500
Ω, is required on SCL if there
are multiple masters on the bus, or if the single master
has an open-drain SCL output. Series resistors in line
with SDA and SCL are optional. Series resistors protect
the digital inputs of the MAX9879 from high voltage
spikes on the bus lines, and minimize crosstalk and
undershoot of the bus signals.
Bit Transfer
One data bit is transferred during each SCL cycle. The
data on SDA must remain stable during the high period
of the SCL pulse. Changes in SDA while SCL is high
are control signals (see the
START and STOP
Conditions section).
START and STOP Conditions
SDA and SCL idle high when the bus is not in use. A
master initiates communication by issuing a START con-
dition. A START (S) condition is a high-to-low transition
on SDA with SCL high. A STOP (P) condition is a low-to-
high transition on SDA while SCL is high (Figure 7).
Table 6. Speaker/Headphone Modes
BIT
DESCRIPTION
LSPKEN
Enable bit for left speaker
RSPKEN
Enable bit for right speaker
HPEN
Enable bit for headphone amplifier
ENA
Enable bit for input A
ENB
Enable bit for input B
SCL
SDA
START
CONDITION
STOP
CONDITION
REPEATED
START CONDITION
START
CONDITION
tHD:STA
tSU:STA
tBUF
tSU:STO
tLOW
tSU:DAT
tHD:DAT
tHIGH
tR
tF
Figure 6. 2-Wire Interface Timing Diagram
SMBus is a trademark of Intel Corp.
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