參數(shù)資料
型號(hào): MAX9867ETJ+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 18/55頁(yè)
文件大?。?/td> 0K
描述: IC STEREO AUD CODEC LP 32TQFN-EP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
類(lèi)型: 立體聲音頻
數(shù)據(jù)接口: I²C,串行
分辨率(位): 18 b
ADC / DAC 數(shù)量: 2 / 2
三角積分調(diào)變:
動(dòng)態(tài)范圍,標(biāo)準(zhǔn) ADC / DAC (db): 85 / 90
電壓 - 電源,模擬: 1.65 V ~ 1.95 V
電壓 - 電源,數(shù)字: 1.65 V ~ 1.95 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 32-WFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 32-TQFN-EP(5x5)
包裝: 帶卷 (TR)
MAX9867
Ultra-Low Power Stereo Audio Codec
______________________________________________________________________________________
25
BITS
FUNCTION
Exact Integer Modes
Allows integer sampling for specific PCLK (prescaled MCLK) frequencies and 8kHz or 16kHz sample rates.
FREQ[3:0]
PCLK (MHz)
LRCLK (kHz)
PCLK/LRCLK
0x00
Normal or PLL mode
0x1–0x7
Reserved
0x8
0x9
12
8
16
1500
750
0xA
0xB
13
8
16
1625
812.5
0xC
0xD
16
8
16
2000
1000
0xE
0xF
19.2
8
16
2400
1200
FREQ
Modes 0x8–0xF are available in either master or slave mode. In slave mode, if the indicated PCLK/LRCLK ratio
cannot be guaranteed, use PLL mode instead.
PLL
PLL Mode Enable
0 = Valid for slave and master mode. The frequency of LRCLK is set by the NI divider bits. In master mode, the
MAX9867 generates LRCLK using the specified divide ratio. In slave mode, the MAX9867 expects an
LRCLK as specified by the divide ratio.
1 = Valid for slave mode only. A digital PLL locks on to any externally supplied LRCLK signal.
Rapid Lock Mode
To enable rapid lock mode, set NI to the nearest desired ratio and set NI[0] = 1 before enabling the interface.
NI
Normal Mode LRCLK Divider
When PLL = 0, the frequency of LRCLK is determined by NI. See Table 5 for common NI values.
NI = (65536 x 96 x fLRCLK)/fPCLK
fLRCLK = LRCLK frequency
fPCLK = Prescaled MCLK internal clock frequency (PCLK)
LRCLK > 24kHz is only valid for MODE = 0 (stereo audio mode). MODE = 1 (voice mode) requires LRCLK
24kHz.
Table 4. Clock Control Registers (continued)
LRCLK (kHz)
MCLK (MHz)
PSCLK
8
16
24
32
44.1
48
11.2896
01
0x116A
0x22D4
0x343F
0x45A9
0x6000
0x687D
12
01
0x1062
0x20C5
0x3127
0x4189
0x5A51
0x624E
12.288
01
0x1000
0x2000
0x3000
0x4000
0x5833
0x6000
13
01
0x0F20
0x1E3F
0x2D5F
0x3C7F
0x535F
0x5ABE
19.2
01
0x0A3D
0x147B
0x1EB8
0x28F6
0x3873
0x3D71
24
10
0x1062
0x20C5
0x1893
0x4189
0x5A51
0x624E
26
10
0x0F20
0x1E3F
0x16AF
0x3C7F
0x535F
0x5ABE
27
10
0x0E90
0x1D21
0x15D8
0x3A41
0x5048
0x5762
Note: Bolded values are exact integers that provide maximum full-scale performance.
Table 5. Common NI Values
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