參數(shù)資料
型號(hào): MAX9856ETL+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 15/46頁(yè)
文件大小: 0K
描述: IC AUDIO CODEC 40TQFN-EP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
類型: 音頻編解碼器
數(shù)據(jù)接口: 串行
分辨率(位): 18 b
ADC / DAC 數(shù)量: 2 / 2
三角積分調(diào)變:
S/N 比,標(biāo)準(zhǔn) ADC / DAC (db): 77 / 91
動(dòng)態(tài)范圍,標(biāo)準(zhǔn) ADC / DAC (db): 85 / 91
電壓 - 電源,模擬: 1.71 V ~ 3.6 V
電壓 - 電源,數(shù)字: 1.71 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 40-WFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 40-TQFN-EP(5x5)
包裝: 帶卷 (TR)
MAX9856
DAC Interface
The MAX9856 DAC is capable of supporting any sam-
ple rate from 8kHz to 96kHz in either master or slave
mode, including all common sample rates (8kHz,
11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz,
44.1kHz, 48kHz, 88.2kHz and 96kHz).
A 15-bit clock divider coefficient must be programmed
into the device to set the DAC sample rate relative to
the prescaled MCLK input (PCLK). This allows high
flexibility in both the MCLK and LRCLK_D frequencies.
In slave mode, the interface accepts any LRCLK_D sig-
nal between 7.8kHz to 100kHz.
There are two speed settings for the DAC set by the
DRATE control bits. The highest rate runs the modulator
at an internal clock rate between 5MHz and 10MHz,
and provides the highest audio performance. The low
rate runs the modulator between 2.5MHz and 5MHz for
reduced power consumption.
The digital audio interface offers full functionality for
several digital audio formats including left-justified, I2S,
and PCM modes (Figure 1). Figure 2 shows the digital
timing for various modes. Table 5 shows the DAC inter-
face registers and descriptions. Table 6 lists the common
DACNI and ADCNI values.
Low-Power Audio CODEC with
DirectDrive Headphone Amplifiers
22
______________________________________________________________________________________
REG
B7
B6
B5
B4
B3
B2
B1
B0
0x04
DWCI
DBCI
DRATE
DDLY
PCM
DHF
WS
0x05
DPLLEN
DACNI[14:8]
0x06
DACNI[7:0]
Table 5. DAC Interface Registers
REGISTER
FUNCTION
DWCI
DAC Word Clock (LRCLK_D) Invert
When PCM = 0:
0—Left-channel data is transmitted while LRCLK_D is low.
1—Right-channel data is transmitted while LRCLK_D is low.
When PCM = 1:
0—Start of a new frame is signified by the falling edge of the LRCLK_D pulse.
1—Start of a new frame is signified by the rising edge of the LRCLK_D pulse.
DBCI
DAC BCLK Invert:
0—SDIN is accepted on the rising edge of BCLK.
1—SDIN is accepted on the falling edge of BCLK.
In master mode:
0—LRCLK_D transitions occur on the falling edge of BCLK.
1—LRCLK_D transitions occur on the rising edge of BCLK.
DRATE
DAC Modulator Rate:
00—Low-power mode
01—Reserved
10—High-performance mode
11—DAC clock disabled
DDLY
DAC Data Delay:
0—The most significant bit of an audio word is latched at the first BCLK edge after the
LRCLK_D transition.
1—The most significant bit of an audio word is latched at the second BCLK edge after the
LRCLK_D transition.
(DDLY = 1 for I2S-compatible mode)
DAC Interface Register Bit Descriptions
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