參數(shù)資料
型號(hào): MAX9856ETL+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 14/46頁(yè)
文件大?。?/td> 0K
描述: IC AUDIO CODEC 40TQFN-EP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
類型: 音頻編解碼器
數(shù)據(jù)接口: 串行
分辨率(位): 18 b
ADC / DAC 數(shù)量: 2 / 2
三角積分調(diào)變:
S/N 比,標(biāo)準(zhǔn) ADC / DAC (db): 77 / 91
動(dòng)態(tài)范圍,標(biāo)準(zhǔn) ADC / DAC (db): 85 / 91
電壓 - 電源,模擬: 1.71 V ~ 3.6 V
電壓 - 電源,數(shù)字: 1.71 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 40-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 40-TQFN-EP(5x5)
包裝: 帶卷 (TR)
MAX9856
Low-Power Audio CODEC with
DirectDrive Headphone Amplifiers
______________________________________________________________________________________
21
Interrupt Enables
Hardware interrupts are reported on the open-drain
IRQ
pin. When an interrupt occurs,
IRQ remains low until the
interrupt is serviced by reading status register 0x00. If a
flag is set, it is reported as a hardware interrupt only if
the corresponding interrupt enable is set. Each bit
enables interrupts for the status flag in the respective bit
location in register 0x00. Table 3 lists the interrupt enable
bit locations and description.
REG
B7
B6
B5
B4
B3
B2
B1
B0
0x02
ICLD
ISLD
IULK
0
IHPOCL
IHPOCR
IJDET
IGPI
Table 3. Interrupt Enable Bit Locations
REG
B7
B6
B5
B4
B3
B2
B1
B0
0x03
0
PSCLK
MAS
BSEL
Table 4. Clock Control Register
BITS
FUNCTION
PSCLK
MCLK Prescaler. Set PSCLK to appropriately divide down MCLK to a usable frequency:
000—Disable clock input
001—10MHz
≤ MCLK ≤ 16MHz (PCLK = MCLK/1)
010—16MHz
≤ MCLK ≤ 20MHz (PCLK = MCLK/1)
011—20MHz
≤ MCLK ≤ 32MHz (PCLK = MCLK/2)
100—32MHz
≤ MCLK ≤ 40MHz (PCLK = MCLK/2)
101—40MHz
≤ MCLK ≤ 60MHz (PCLK = MCLK/4)
110—Reserved
111—Reserved
MAS
Master Mode. Selects between master and slave operation:
0 = Slave mode (BCLK, LRCLK_D, and LRCLK_A are inputs)
1 = Master mode (BCLK, LRCLK_D, and LRCLK_A are outputs)
BSEL
BCLK Select. Configures BCLK when operating in master mode. Set BSEL to be a sufficiently high frequency to
fully clock in all data bits for both the DAC and ADC, if operating at different sample rates:
000—Off
001—Off
010—BCLK = 48 x LRCLK_D (recommended if the DAC and ADC operate at the same rate)
011—BCLK = 48 x LRCLK_A
100—BCLK = PCLK/2 (recommended if the DAC and ADC are not operating at the same rate)
101—BCLK = PCLK/4
110—BCLK = PCLK/8
111—BCLK = PCLK/16
Clock Control Register Bit Description
Clock Control
The MAX9856 can work with a master clock supplied
from any system clock (MCLK) within the range of
10MHz to 60MHz range. A clock prescaler divides by
1, 2, or 4 to create an internal clock (PCLK) in the
10MHz to 20MHz range.
There are two clock-generation circuits that operate
independently for the ADC and DAC path, allowing the
ADC and DAC to be operated at different sample rates.
BCLK services the LRCLK signals for both the ADC and
DAC. When the ADC and DAC operate at different
LRCLK rates, BCLK should be set appropriately for the
higher sample rate. The number of clock cycles per
frame must be greater than or equal to the configured
bit depth.
The MAX9856 digital audio interface can operate in
either master or slave mode. In master mode, the
MAX9856 generates the BCLK and LRCLK signals,
which control the data flow on the digital audio inter-
face. In slave mode, the external master device gener-
ates the BCLK and LRCLK signals. See Table 4.
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