
M
High-Efficiency, Low-I
Q
PMIC with
Dynamic Core for PDAs and Smartphones
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27
Note that the pole cancellation does not have to be
exact. R
C
x C
C
need only be within 0.75 to 1.25 times
R
LOAD
x C
OUT
. This provides flexibility in component
selection.
If the output-filter capacitor has significant ESR, a zero
occurs at:
Z
ESR
= 1 / (2
π
x C
OUT
x R
ESR
)
If Z
ESR
> f
C
, it can be ignored, as is typically the case
with ceramic or polymer output capacitors. If Z
ESR
is
less than f
C
, it should be cancelled with a pole set by
capacitor C
P
connected from CC_ to GND:
C
P
= C
OUT
R
ESR
/ R
C
If C
P
is calculated to be < 10pF, it can be omitted.
Optimizing Transient Response
In applications that require load-transient response to
be optimized in favor of minimum component values,
increase the output-filter capacitor to increase the R in
the compensation RC. From the equations in the previ-
ous section, doubling the output cap allows a doubling
of the compensation R, which then doubles the tran-
sient gain.
Applications Information
Extending the Maximum Core
Voltage Range
The V3 output can be serially programmed to supply
from 0.7V to 1.475V in 25mV steps. In some cases, a
higher CPU core voltage may be desired. The V3 volt-
age range can be increased by adding two resistors as
shown in Figure 7.
R24 and R25 add a small amount of gain. They are set
so that an internally programmed value of 1.475V
results in a higher actual output at V3. The resistors
shown in Figure 1 set a maximum output of 1.55V, 1.6V,
or 1.65V. All output steps are shifted and the step size
is also slightly increased.
The output voltage for each programmed step of V3 in
Figure 7 is:
V3 = V3
PROG
+ (R24[(V3
PROG
/ R25) +
(V3
PROG
/ 185,500)])
where V3 is the actual output voltage, V3PROG is the
original programmed voltage from the “OUTPUT (V)”
column in Table 2, and 185,500 is the internal resis-
tance of the FB3 pin.
Backup-Battery and V7 Configurations
The MAX8588 includes a backup-battery connection,
BKBT, and an output, V7. These can be utilized in differ-
ent ways for various system configurations.
Primary Backup Battery
A connection with a primary (nonrechargeable) lithium
coin cell is shown in Figure 6. The lithium cell connects to
BKBT directly. V7 powers the CPU VCC_BATT from either
V1 (if enabled) or the backup battery. It is assumed
whenever the main battery is good, V1 is on (either with
its DC-DC converter or sleep LDO) to supply V7.
No Backup Battery (or Alternate Backup)
If no backup battery is used, or if an alternate backup
and VCC_BATT scheme is used that does not use the
MAX8588, then BKBT should be biased from IN with a
small silicon diode (1N4148 or similar, as in Figure 8).
BKBT must still be powered when no backup battery is
used because
DBO
,
RSO
, and POK require this supply
to function. If BKBT is not powered, these outputs do
not function and are high impedance.
PV3
STEP-DOWN
PWM
REG3
**
OTHER R24 VALUES:
R24 = 5.5k
, V3: 0.759V TO 1.60V
R24 = 7.7k
, V3: 0.783V TO 1.65V
LX3
PG3
FB3
185.5k
V3
VCC_CORE
1.55V MAX
TO BATT
R25
100k
R24**
3.3k
MAX8588
Figure 7. Addition of R24 and R25 increases maximum core
voltage. The values shown raise the maximum core from
1.475V to 1.55V.