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參數(shù)資料
| 型號： | MAX8588ETM |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | High-Efficiency, Low-IQ PMIC with Dynamic Core for PDAs and Smartphones |
| 中文描述： | 7-CHANNEL POWER SUPPLY SUPPORT CKT, QCC48 |
| 封裝： | 6 X 6 MM, 0.80 MM HEIGHT, TQFN-48 |
| 文件頁數(shù)： | 23/31頁 |
| 文件大?。?/td> | 572K |
| 代理商： | MAX8588ETM |
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M
High-Efficiency, Low-I
Q
PMIC with
Dynamic Core for PDAs and Smartphones
______________________________________________________________________________________
23
Bit Transfer
One data bit is transferred during each SCL clock
cycle. The data on SDA must remain stable during the
high period of the SCL clock pulse. Changes in SDA
while SCL is high are control signals (see the
START
and STOP Conditions
section). Both SDA and SCL idle
high when the bus is not busy.
START and STOP Conditions
When the serial interface is inactive, SDA and SCL idle
high. A master device initiates communication by issu-
ing a START condition. A START condition is a high-to-
low transition on SDA with SCL high. A STOP condition
is a low-to-high transition on SDA while SCL is high
(Figure 5). A START condition from the master signals
the beginning of a transmission to the MAX8588. The
master terminates transmission by issuing a not
acknowledge followed by a STOP condition (see the
Acknowledge Bit
section). The STOP condition frees
the bus.
When a STOP condition or incorrect address is detect-
ed, the MAX8588 internally disconnects SCL from the
serial interface until the next START condition, minimiz-
ing digital noise and feedthrough.
Acknowledge Bit (ACK)
The acknowledge bit (ACK) is the ninth bit attached to
every 8-bit data word. The receiving device always
generates ACK. The MAX8588 generates an ACK when
receiving an address or data by pulling SDA low during
the ninth clock period. Monitoring ACK allows for
detection of unsuccessful data transfers. An unsuc-
cessful data transfer occurs if a receiving device is
busy or if a system fault has occurred. In the event of
an unsuccessful data transfer, the bus master should
reattempt communication at a later time.
Serial Address
A bus master initiates communication with a slave
device by issuing a START condition followed by the
7-bit slave address (Table 3). When idle, the MAX8588
waits for a START condition followed by its slave
address. The serial interface compares each address
value bit by bit, allowing the interface to power down
immediately if an incorrect address is detected.
The LSB of the address word is the read/write (R/
W
) bit.
R/
W
indicates whether the master is writing or reading
(RD/
W
0 = write, RD/
W
1 = read). The MAX8588 only
supports the SEND BYTE format; therefore, RD/
W
is
required to be 0.
After receiving the proper address, the MAX8588
issues an ACK by pulling SDA low for one clock cycle.
The MAX8588 has two user-programmed addresses
(Table 3). Address bits A6 through A1 are fixed, while
A1 is controlled by SRAD. Connecting SRAD to GND
sets A1 = 0. Connecting ADD to IN sets A1 = 1.
V3 Output Ramp-Rate Control
When V3 is dynamically changed with the serial inter-
face, the output voltage changes at a rate controlled by
a capacitor (C
RAMP
) connected from RAMP to ground.
The voltage change is a conventional RC exponential
described by:
Vo(t) = Vo(0) + dV(1 – exp(-t / (100k
C
RAMP
)))
SCL
A
B
C
D
E
F
G
H
I
J
K
SDA
t
SU:STA
t
HD:STA
t
LOW
t
HIGH
t
SU:DAT
t
HD:DAT
t
SU:STO
t
BUF
A = START CONDITION
B = MSB OF ADDRESS CLOCKED INTO SLAVE
C = LSB OF ADDRESS CLOCKED INTO SLAVE
D = R/W BIT CLOCKED INTO SLAVE
E = SLAVE PULLS SMB DATA LINE LOW
L
M
F = ACKNOWLEDGE BIT CLOCKED INTO MASTER
G = MSB OF DATA CLOCKED INTO SLAVE (OP/SUS BIT)
H = LSB OF DATA CLOCKED INTO SLAVE
I = SLAVE PULLS SMB DATA LINE LOW
J = ACKNOWLEDGE CLOCKED INTO MASTER
K = ACKNOWLEDGE CLOCK PULSE
L = STOP CONDITION, DATA EXECUTED BY SLAVE
M = NEW START CONDITION
Figure 5. I
2
C-Compatible Serial-Interface Timing Diagram
Table 3. Serial Address
SRAD
A7
A6
A5
A4
A3
A2
A1
A0
RD/
W
0
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
0
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX8588ETM+ | 功能描述:PMIC 解決方案 High-Efficiency Low IQ PMIC RoHS:否 制造商:Texas Instruments 安裝風格:SMD/SMT 封裝 / 箱體:QFN-24 封裝:Reel |
| MAX8588ETM+T | 功能描述:PMIC 解決方案 High-Efficiency Low IQ PMIC RoHS:否 制造商:Texas Instruments 安裝風格:SMD/SMT 封裝 / 箱體:QFN-24 封裝:Reel |
| MAX8588ETM-T | 功能描述:PMIC 解決方案 High-Efficiency Low IQ PMIC RoHS:否 制造商:Texas Instruments 安裝風格:SMD/SMT 封裝 / 箱體:QFN-24 封裝:Reel |
| MAX858C/D | 功能描述:直流/直流開關(guān)轉(zhuǎn)換器 DICE SALES DICE RoHS:否 制造商:STMicroelectronics 最大輸入電壓:4.5 V 開關(guān)頻率:1.5 MHz 輸出電壓:4.6 V 輸出電流:250 mA 輸出端數(shù)量:2 最大工作溫度:+ 85 C 安裝風格:SMD/SMT |
| MAX858CPA | 功能描述:直流/直流開關(guān)轉(zhuǎn)換器 RoHS:否 制造商:STMicroelectronics 最大輸入電壓:4.5 V 開關(guān)頻率:1.5 MHz 輸出電壓:4.6 V 輸出電流:250 mA 輸出端數(shù)量:2 最大工作溫度:+ 85 C 安裝風格:SMD/SMT |
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