參數(shù)資料
型號: MAX8588ETM
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 電源管理
英文描述: High-Efficiency, Low-IQ PMIC with Dynamic Core for PDAs and Smartphones
中文描述: 7-CHANNEL POWER SUPPLY SUPPORT CKT, QCC48
封裝: 6 X 6 MM, 0.80 MM HEIGHT, TQFN-48
文件頁數(shù): 15/31頁
文件大小: 572K
代理商: MAX8588ETM
M
High-Efficiency, Low-I
Q
PMIC with
Dynamic Core for PDAs and Smartphones
______________________________________________________________________________________
15
Pin Description (continued)
PIN
NAME
FUNCTION
16
PV2
REG2 Power Input. Bypass to PG2 with a 4.7μF or greater low-ESR capacitor. PV1, PV2, PV3, and IN must
connect together externally.
17
LX2
REG2 Switching Node. Connects to REG2 inductor.
18
PG2
REG2 Power Ground. Connect directly to a power-ground plane. Connect PG1, PG2, PG3, and GND
together at a single point as close to the IC as possible.
19
IN
Main Battery Input. This input provides power to the IC.
20
RAMP
V3 Ramp-Rate Control. A capacitor connected from RAMP to GND sets the rate-of-change when V3 is
changed. The output impedance of RAMP is 100k
. FB3 regulates to 1.28 x V
RAMP
.
Analog Ground
Reference Output. Output of the 1.25V reference. Bypass to GND with a 0.1μF or greater capacitor.
Low-Noise LDO Bypass. Low-noise bypass pin for V4 LDO. Connect a 0.01μF capacitor from BYP to GND.
21
22
23
GND
REF
BYP
24
DBO
Dead or Missing Battery Output.
DBO
is an open-drain output that goes low when IN is below the threshold
set by DBI.
DBO
does not deactivate any regulator outputs.
DBO
is expected to connect to nBATT_FAULT
on Intel CPUs.
25
ON2
On/Off Input for REG2. Drive high to turn on. When enabled, the REG2 output soft-starts. ON2 has hysteresis
so an RC can be used to implement manual sequencing with respect to other inputs. It is expected that ON1,
ON2, and ON6 are connected to SYS_EN.
26
ON4
On/Off Input for REG4. Drive high to turn on. When enabled, the REG4 output activates. ON4 has hysteresis
so an RC can be used to implement manual sequencing with respect to other inputs. It is expected that ON4
is connected to PWR_EN.
27
V4
Also Known as VCC_PLL. 1.3V, 35mA linear-regulator output for PLL. Regulator input is IN45.
28
IN45
Power Input to V4 and V5 LDOs. Typically connected to V2, but can also connect to IN or another voltage
from 2.5V to V
IN
.
Also Known as VCC_SRAM. 1.1V, 35mA linear-regulator output for CPU SRAM. Regulator input is IN45.
29
V5
30
ON5
On/Off Input for REG5. Drive high to turn on. When enabled, the MAX8588 soft-starts the REG5 output. ON5
has hysteresis so an RC can be used to implement manual sequencing with respect to other inputs. It is
expected that ON5 is connected to PWR_EN.
31
PG3
REG3 Power Ground. Connect directly to a power-ground plane. Connect PG1, PG2, PG3, and GND
together at a single point as close to the IC as possible.
32
LX3
REG3 Switching Node. Connects to the REG3 inductor.
33
PV3
REG3 Power Input. Bypass to PG3 with a 4.7μF or greater low-ESR ceramic capacitor. PV1, PV2, PV3, and IN
must connect together externally.
34
ON3
On/Off Input for REG3 (Core). Drive high to turn on. When enabled, the REG3 output ramps up. ON3 has
hysteresis so an RC can be used to implement manual sequencing with respect to other inputs. It is
expected that ON3 is driven from CPU SYS_EN.
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