
M
Flash Programmable 12-Bit Integrated
Data-Acquisition Systems
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29
Note:
Do not write to the same location more than twice
before the next page/mass erase operation.
Flash Memory Page Erase
The page erase operation sets all bits within the page
to
“
1
”
s. To erase a page from Flash memory, load the
page address into SFR EEAH, register EEAL is not
used. Then write 5AH to EESTCMD. The execution time
for page erase is 9.4ms (typ) and is independent of the
CPU clock.
Note:
Do not attempt to apply read, write, or page-
erase operations to the flash memory block in which the
CPU is currently executing program instructions.
External Flash Memory Programming
The MAX7651/MAX7652 are normally shipped with the
internal Flash memory blocks fully erased (all bits set to
1) and ready for external programming. External write,
read (verify), and mass-erase operations are available.
Flash memory addresses for either the upper or lower
8-kbyte blocks are specified at Ports 1 and 2.
Before applying any external Flash memory operations,
power-up the MAX7651/MAX7652 with RST asserted.
ALE,
PSEN
, and ports P1
–
P3 are pulled high with weak
resistive pullups. Port P0 requires 10k
external pull-
ups. Wait at least 10ms for the oscillator and internal
circuitry to stabilize. The program, verify and mass-
erase flash memory programming steps are outlined
below.
Note:
Failure to follow proper power-up conditions or
the specified flash memory programming steps can
result in loss of flash data integrity.
External Flash Memory Program (Table 2)
Erase operations. Set all bits to
“
1
”
. After a byte has been
programmed it must be erased before it is re-written.
1) Power-up the device with RST asserted and allow
ALE and
PSEN
to float to the
“
1
”
state (they will be
internally pulled-up during RST assertion).
2) Wait 10ms for the internal bandgap and oscillator to
stabilize.
3) Apply the memory location on the address lines at
ports 1 and 2.
4) Apply data to the data lines at port 0.
5) Raise
EA
/ V
PP
to DV
DD
and pull
PSEN
low.
6) Set P2.6, P2.7, P3.6, and P3.7 to the levels shown in
Table 2.
7) Set P2.5 low or high for the lower or higher 8kB Flash
memory block.
8) Force ALE /
PROG
low. P3.4 (READY) will go low to
indicate a write in progress.
9) When P3.4 returns high (write complete after
approximately 63μs), set ALE /
PROG
high.
10)Power-down sequence.
A) Remove drive from and allow
PSEN
and
ALE/
PROG
to float high.
B) Pull
EA
low.
C) High-Z all digital pins.
D) Remove power from all power pins.
Note:
Do not write to the same location more than twice
before the next page/mass erase operation.
External Flash Memory Verify (Table 2)
External Verify:
If lock bits LB1 and LB2 have not been programmed,
the programmed flash array(s) can be read back
through the address and data lines for verification. The
lock bits cannot be verified directly. Verification of the
lock bits is achieved by observing that their features
are enabled.
External verify (readback) power-up sequence:
1) Power-up the MAX7651/MAX7652 with RST assert-
ed, allow ALE and
PSEN
to float to the
“
1
”
state (they
will be internally pulled-up during RST assertion).
Wait 10ms for the internal bandgap and oscillator to
stabilize.
2) Pull
PSEN
LOW,
EA
HIGH, ALE HIGH, and set P2.6,
P2.7, P3.6, P3.7, P2.5, as per
Flash Programming
Modes (Table 2) for reading either LOWER or UPPER
flash memory block.
Note:
P2.7 is cycled low/high to perform a FLASH read
operation. Minimum low time for P2.7 is ten clock
cycles.
External verify power-down sequence:
1) Power-down sequence
A)Remove drive from and allow
PSEN
and ALE/
PROG
to float high.
B) Pull
EA
low.
C) Hi-z all digital pins.
D) Remove power from all power pins.