參數(shù)資料
型號: MAX7651
廠商: Maxim Integrated Products, Inc.
英文描述: Flash Programmable 12-Bit Integrated Data-Acquisition Systems
中文描述: 閃存、可編程、12位、集成數(shù)據(jù)采集系統(tǒng)
文件頁數(shù): 16/36頁
文件大?。?/td> 479K
代理商: MAX7651
M
Flash Programmable 12-Bit Integrated
Data-Acquisition Systems
16
______________________________________________________________________________________
Pin Description (continued)
PIN
NAME
FUNCTION
P0.5: Bit 5 for General Purpose I/O Port 0
AD5: Bit 5 for Internal Flash Memory Data or external memory I/O
P0.6: Bit 6 for General Purpose I/O Port 0
AD6: Bit 6 for Internal Flash Memory Data or external memory I/O
P0.7: Bit 7 for General Purpose I/O Port 0 (most significant bit)
AD7: Bit 7 for Internal Flash Memory Data or external memory I/O
46
P0.5/
AD5
47
P0.6/
AD6
48
P0.7/
AD7
P1.0: Bit 0 for General Purpose I/O Port 1 (least significant bit)
T2: Timer 2 External Input
T2OUT: Timer 2 External Output
AD0: Bit 0 for Internal Flash Memory Address
P1.1: Bit 1 for General Purpose I/O Port 1
T2EX: Timer 2 External Capture/Reload Trigger
AD1: Bit 1 for Internal Flash Memory Address
P1.2: Bit 2 for General Purpose I/O Port 1
RXD1: Receive Serial Input for UART 1
AD2: Bit 2 for Internal Flash memory Address
P1.3: Bit 3 for General Purpose I/O Port 1
TXD1: Transmit Serial Input for UART 1
AD3: Bit 3 for Internal Flash Memory Address
P1.4: Bit 4 for General Purpose I/O Port 1
AD4: Bit 4 for Internal Flash Memory Address
P1.5: Bit 5 for General Purpose I/O Port 1
AD5: Bit 5 for Internal Flash Memory Address
P1.6: Bit 6 for General Purpose I/O Port 1
AD6: Bit 6 for Internal Flash Memory Address
P1.7: Bit 7 for General Purpose I/O Port 1
AD7: Bit 7 for Internal Flash Memory Address
EA
: Connect to DGND to use external ROM. Connect
EA
to DV
DD
for internal flash memory.
V
PP
: Flash Programming Voltage (external flash programming mode only)
Active High Reset. Connected to an internal 130k
pulldown resistor. Connect a 2.2μF (typ) capacitor from
DV
DD
to RST.
Clock Output. Connect a crystal across XTAL1 and XTAL2. The on-chip clock signal is not available at
XTAL2. Leave XTAL2 unconnected when XTAL1 is driven with an external clock.
Clock Input. Connect a crystal across XTAL1 and XTAL2. Alternatively, drive XTAL1 with a CMOS-
compatible clock and leave XTAL2 unconnected.
Digital Ground. Connect pins 27, 39, and 61 together.
Positive Digital Supply Voltage. Bypass with a 0.1μF in parallel with a 10μF low ESR capacitor to DGND.
Connect pins 28, 40 and 62 together.
Test Point. Must be connected to DGND.
Analog Common Input. Negative differential input relative to AIN_ for single-ended
measurements (see Table 6). Connect to AV
DD
/2 for maximum input range.
49
P1.0/T2/
T2OUT/
AD0
50
P1.1/
T2EX/
AD1
51
P1.2/
RXD1/
AD2
52
P1.3/
TXD1/
AD3
53
P1.4/
AD4
54
P1.5/
AD5
55
P1.6/
AD6
56
P1.7/
AD7
57
EA
/V
PP
58
RST
59
XTAL2
60
XTAL1
61
DGND
62
DV
DD
63
TEST
64
ACOM
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