
M
Flash Programmable 12-Bit Integrated
Data-Acquisition Systems
26
______________________________________________________________________________________
WD1
0
0
1
1
WD0
0
1
0
1
INTERRUPT TIMOUT
2
16
clocks
2
19
clocks
2
22
clocks
2
25
clocks
TIME (ms)
5.461
43.691
349.525
2796.000
RESET TIMOUT
2
16
+ 512 clocks
2
19
+ 512 clocks
2
22
+ 512 clocks
2
25
+ 512 clocks
TIME (ms)
5.474
43.734
349.567
2796.042
Table 16. Watchdog Interrupt and Reset Times (f
CK
= 12MHz)
Serial Interface Ports
The MAX7651/MAX7652 each have two serial inter-
faces that operate according to the 8051 industry stan-
dard. Serial Port 0 uses SFRs SCON0 and SBUF0 for
control and buffer functions. Serial Port 1 uses SFRs
SCON1 and SBUF1 with identical bit functionality. See
the MAX7651/MAX7652
Programmer
’
s Reference
Manual
for details concerning serial-port data opera-
tions and timing information.
Timers/Counters
The MAX7651/MAX7652 have three timer/counters that
function in several different modes for applications
such as UART baud-rate control. All three timer/coun-
ters operate according to the 8051 industry standard.
Specifically, the control (TCON), mode (TMOD), timer-0
parameter (TL0, TH0), Timer1 parameter (TL1, TH1),
and Timer-2 parameter (TL2, TH2, RCAP2L, RCAP2H)
SFRs have conventional formats. See the MAX7651/
MAX7652
Programmer
’
s Reference Manual
for informa-
tion concerning timer/counter applications.
Crystal Oscillator
The MAX7651/MAX7652 each have a single-stage invert-
er (Input at XTAL1, Output at XTAL2) that supports a crys-
tal controlled oscillator. The crystal oscillator frequency
should be between 1 and 12 MHz.
Note:
External flash memory programming requires a
minimum crystal oscillator frequency of 4MHz.
Crystal Specification:
Rs(typ)
Rs(max)
Load Capacitance
Oscillation Mode
Frequency
Tolerance
Holder Capacitance
Motional Inductance (typ)
Motional capacitance (typ)
25
–
40
150
10
–
15pF
Fundamental
12,000MHz (max)
±
0.01%
3pF
50mH
0.0035pF
BIT 7
(MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
(LSB)
PWDB7
PWDB6
PWDB5
PWDB4
PWDB3
PWDB2
PWDB1
PWDB0
Table 14. Pulse-Width Data B (PWDB) Format
—
SFR address DCH
BIT 7
(MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
(LSB)
PWON
—
—
—
—
—
PWENA
PWENB
BIT
NAME
DESCRIPTION
7
PWON
Pulse-Width-Modulator Enable. Set PWON to 1 to enable the divide-by-two, PWPS prescaler,
and modulo-255 counter circuit functions.
6
–
2
1
0
—
Not used
PWM Output A Enable. Set to 1 to enable PWM output A.
PWM Output B Enable. Set to 1 to enable PWM output B.
PWENA
PWENB
Table 15. Pulse-Width-Modulator Control (PWMC) Format
—
SFR Address FEH